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Design Verification Engineer - Interface IP

Etched

Company websiteetched.com (Etched, opens in new tab)

Base salary $150K  to $350K

Employer-published annual base salary, USD. Advertised base range in Austin, TX

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  • LocationAustin, TX
  • WorkplaceOn-site
  • Status at last checkSource accepting applications when checked
  • Last checked (10 min ago) · observed since

About this job

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.

Key responsibilities

  • End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors

  • Understand vendor IP configurations and handle handshake with internal IP team

  • Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.

  • Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.

  • Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.

You may be a good fit if you have

  • 5+ years of design verification experience

  • You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.

  • You have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches.

  • You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.

  • You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.

  • You collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights.

Strong candidates may also have experience with

  • Experience handling vendors and integration of IP/VIP’s

  • UVM/System Verilog

Benefits

  • Medical, dental, and vision packages with generous premium coverage

    • $500 per month credit for waiving medical benefits

  • Various wellness benefits covering fitness, mental health, and more

  • Daily lunch + dinner in our office

  • Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

We greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.

Source: Etched on Ashby · View original posting (opens in new tab)

This range next to 6 other live Etched roles with the nearest advertised base floor
Chart as a table
This range next to 6 other live Etched roles with the nearest advertised base floor
RolePublished base
Design Verification Engineer - Interface IP (this listing)$150K - $350K
Design Verification Engineer - Internal IP$150K - $350K
RTL Design Engineer$150K - $370K
ECAD Librarian$150K - $300K
IT Engineer$150K - $300K
Product Quality Engineer$150K - $275K
Design Verification Engineer - Internal IP$150K - $350K

Same $100K to $400K scale as every card. All Etched roles · How to read the bar

Observed changes

  1. Began meeting the published-salary criteria
  2. First observed on the employer's board
  3. Advertised base range changed
Observed since
Employer-stated posting date
2026-04-16
Where this pay comes from

Location as the employer wrote it: Austin

USD 150,000 – 350,000 · 1 YEAR · Salary

Method
Structured pay field published by the employer
Checked
Rule set
us-base-v2

The employer's job board publishes this pay as a dedicated data field. We read the field directly; no interpretation was needed.

What we verified

  • The pay figures come from the employer's own listing, quoted exactly above.
  • The pay is an annual base salary in US dollars with a minimum of at least $100,000.
  • The role was publicly listed on the employer's job board when last checked.

We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.