Post-Silicon Validation Engineer
Company websiteetched.com (Etched, opens in new tab)
Base salary $160K to $350K
Employer-published annual base salary, USD. Advertised base range in San Jose, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSan Jose, CA
- WorkplaceOn-site
- Status at last checkSource accepting applications when checked
- Last checked (2 h ago) · observed since
About this job
About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
We are seeking a highly skilled and motivated Post Silicon Validation Engineer to join our dynamic team. The ideal candidate will be responsible for bringing up, validating, and characterizing ASICs from first silicon through the production ramp. This role is crucial in ensuring functional correctness, performance, and reliability of our AI/ML accelerator hardware, enabling successful deployment of our cutting-edge products.
Key Responsibilities
Drive early bring-up of first silicon, including boot, initialization, and debug of ASICs.
Perform deep-dive debug of silicon issues across RTL, firmware, and system levels.
Collaborate closely with design, verification, and board teams to root-cause and resolve functional and electrical issues.
Validate and characterize custom IP blocks and accelerator components.
Execute functional and performance validation of compute units and specialized processing elements.
Conduct IP-level and full-chip stress testing and corner case analysis to ensure robust operation.
Develop and extend post-silicon validation infrastructure, automation, and test suites.
Implement efficient result capture, analysis, and regression frameworks.
Utilize lab instrumentation (oscilloscopes, analyzers, BERTs, pattern generators) for detailed signal and system characterization.
Define validation strategies and coverage metrics across design blocks and subsystems.
Partner with RTL, DFT, ATE, firmware, and system architecture teams to ensure smooth transition from pre-silicon verification to post-silicon validation.
Provide critical feedback on test escapes, yield issues, and silicon errata, influencing silicon revisions and firmware/driver workarounds.
You may be a good fit if you have
7+ years of experience in post-silicon validation, bring-up, and debug of ASICs (preferably including AI/ML accelerators)
Proven expertise in early silicon bring-up, debug, and validation
Deep knowledge of peripheral interfaces and board-level debug
Proficiency in C, Python, and scripting for validation automation
Hands-on expertise with oscilloscopes, logic/protocol analyzers, and other validation lab tools
Familiarity with firmware, bootloaders, and low-level silicon debug environments
Strong problem-solving, analytical, and collaboration skills across hardware and software teams
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's preferred)
Strong candidates may also have experience with
Low-speed peripheral interfaces (I2C, SPI, UART, JTAG)
High-speed protocols (PCIe, Ethernet)
Memory subsystems (HBM, DDR)
Performance and thermal characterization
AI/ML model profiling and workload correlation
System-level validation of accelerators or server platforms
Benefits
Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2.5k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office
Unlimited compute budget subject to ROI justification
How we’re different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.
Source: Etched on Ashby · View original posting (opens in new tab)
This listingPost-Silicon Validation Engineer$160K to $350K
Design Verification Engineer - Internal IP$150K to $350K
RTL Design Engineer$150K to $370K
ECAD Librarian$150K to $300K
IT Engineer$150K to $300K
Product Quality Engineer$150K to $275K
Design Verification Engineer - Internal IP$150K to $350K
Chart as a table
| Role | Published base |
|---|---|
| Post-Silicon Validation Engineer (this listing) | $160K - $350K |
| Design Verification Engineer - Internal IP | $150K - $350K |
| RTL Design Engineer | $150K - $370K |
| ECAD Librarian | $150K - $300K |
| IT Engineer | $150K - $300K |
| Product Quality Engineer | $150K - $275K |
| Design Verification Engineer - Internal IP | $150K - $350K |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Advertised base range changed
- Observed since
- Employer-stated posting date
- 2025-10-13
Where this pay comes from
Location as the employer wrote it: San Jose
USD 160,000 – 350,000 · 1 YEAR · Salary
- Method
- Structured pay field published by the employer
- Checked
- Rule set
- us-base-v2
The employer's job board publishes this pay as a dedicated data field. We read the field directly; no interpretation was needed.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
