ASIC Design Engineer
Company websitenvidia.com (NVIDIA, opens in new tab)
Base salary $116,000 to $218,500
Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSanta Clara, CA
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (23 min ago) · observed since
About this job
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
At NVIDIA, our passion for innovative technology and dedication to excellence guide us. As an ASIC Design Engineer, you will build powerful SoC and GPU products. These products support everything from consumer graphics to self-driving cars and artificial intelligence. You will be part of a skilled engineering team pushing the boundaries of computing’s future.
What you'll be doing:
Drafting microarchitecture documents and implementing high-performance, and area and power-efficient RTL to meet strictly defined development targets and specifications.
Analyzing architectural trade-offs based on features, performance requirements, and area/power constraints.
Crafting micro-architecture, implementing them in RTL, and delivering fully verified, synthesis/timing clean builds.
Collaborating closely with architects, other designers, and pre and post silicon verification teams to deliver world-class RTL builds.
Working on a diverse list of IPs, including GPU's time distribution system, engine scheduler, interrupt controllers, and copy engines.
Assisting the silicon bring-up team in debugging and post-silicon validation activities.
What we need to see:
BS/MS Degree or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science.
2+ years of relevant RTL design work experience.
Strong in micro-architecture and RTL development (Verilog), as well as entire front-end flows including logic synthesis, power, and timing analysis.
Exposure to Digital systems and VLSI design, Computer Architecture, and Computer Arithmetic.
Strong coding skills in Perl, Python, or other industry-standard scripting languages.
Excellent interpersonal skills and a proven ability to work well in a team.
Ways to stand out from the crowd:
Strong C/C++ skills.
Experience in multi clock domains and asynchronous logic, interface protocols and arbitration schemes.
Outstanding debugging, problem-solving, and analytical abilities.
116,000 USD – 189,750 USD for Level 2; and 136,000 USD – 218,500 USD for Level 3.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 8, 2026.This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.Source: NVIDIA on Workday · View original posting (opens in new tab)
Pay in context
This role's base floor ($116,000) is above 15% of the 2,032 Engineering (non-software) roles in California listed on this site; 12 others list the same floor. Their median floor is $146,200; the middle half runs from $124,579 to $173,000.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 6, 2026.
This listingASIC Design Engineer$116,000 to $218,500
Global Virtual Card Payment Administrator$116,000 to $195,500
Forward Deployed Engineer - Finance$116K to $230K
Customer Solutions Architect, Applications Engineering$116,000 to $189,750
Senior Revenue Accountant – Revenue Accounting Operations$116,000 to $195,500
ASIC Design Engineer – Clocks IP$116,000 to $218,500
Deep Learning Compiler Verification Engineer$116,000 to $189,750
Chart as a table
| Role | Published base |
|---|---|
| ASIC Design Engineer (this listing) | $116,000 - $218,500 |
| Global Virtual Card Payment Administrator | $116,000 - $195,500 |
| Forward Deployed Engineer - Finance | $116K - $230K |
| Customer Solutions Architect, Applications Engineering | $116,000 - $189,750 |
| Senior Revenue Accountant – Revenue Accounting Operations | $116,000 - $195,500 |
| ASIC Design Engineer – Clocks IP | $116,000 - $218,500 |
| Deep Learning Compiler Verification Engineer | $116,000 - $189,750 |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-11-04
Where this pay comes from
Location as the employer wrote it: US, CA, Santa Clara (Levels 2-3 combined)
116,000 USD – 189,750 USD for Level 2; and 136,000 USD – 218,500 USD for Level 3.
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
