Design Engineer - STA
Company websitebroadcom.com (Broadcom, opens in new tab)
Base salary $109,700 to $175,500
Employer-published annual base salary, USD. Advertised base range in United States
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationUnited States
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (8 min ago) · observed since
About this job
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Job Description:
Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products. This position offers the opportunity to work on high-performance SoC designs operating at speeds exceeding 1 GHz, from concept through production.
Role Overview
This STA Engineering role focuses on chip-level timing architecture, analysis, and closure for advanced ASICs in deep sub-micron technologies. The position provides hands-on experience with the latest 3 nm and smaller process nodes and involves working across multiple design hierarchies to define, validate, and sign off complex timing environments for AI, computing, and networking SoCs.
Key Responsibilities
Develop, validate, and maintain timing constraints for complex SoC designs across multiple modes and corners.
Perform static timing analysis (STA) using industry-standard tools such as Synopsys PrimeTime or Cadence Tempus.
Define and execute timing signoff methodologies, including process corners, derates, and uncertainties.
Conduct pre- and post-route timing analysis, quality of results (QoR) evaluations, and closure verification.
Generate and validate timing ECOs to achieve signoff-quality closure across PVT corners.
Automate timing flows and analysis using Tcl and scripting languages such as Perl or Python.
Collaborate with physical design, synthesis, and clock teams to ensure timing convergence and cross-domain consistency.
Analyze and debug timing violations, signal integrity issues, and clock network challenges.
Support power and performance optimization through informed timing analysis and constraint tuning.
Ensure full compliance with timing signoff checklists, methodology, and documentation.
Technical Skills / Background
Deep understanding of VLSI design principles and ASIC physical design fundamentals.
Working knowledge of PLLs, clock network design, and timing elements such as flip-flops, latches, and memories.
Proficiency in timing constraint creation, debugging, and validation.
Strong understanding of RC networks, signal integrity, crosstalk delay, and noise analysis.
Familiar with setup/hold analysis, multi-mode multi-corner (MMMC) timing, and ECO convergence.
Exposure to advanced STA techniques, including POCV/SOCV/LVF, PBA, and SPICE correlation.
Knowledge of timing libraries (CCS/ECSM/NLDM) and multi-input switching (MIS) effects.
Coding & Tool Proficiency
Strong experience with Tcl scripting and Linux/UNIX environments.
Proficiency in Python, Perl, or Ruby preferred.
Hands-on experience with Synopsys and/or Cadence STA tools highly desirable.
Collaboration and Leadership
Excellent communication, analytical, and problem-solving abilities.
Ability to work effectively with external customers, cross-functional and global design teams.
Skilled at organizing and presenting large data sets, prioritizing tasks, and driving to closure.
Demonstrates independent decision-making and strong engineering judgment.
Provides technical leadership, mentoring, and initiative in methodology improvements.
Education and Experience
BS in Electrical or Computer Engineering with 8+ years of relevant experience, or
MS in Electrical or Computer Engineering with 6+ years of relevant experience.
Compensation and Benefits
The annual base salary range for this position is USD 109,700.00 To USD 175,500.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Source: Broadcom on Workday · View original posting (opens in new tab)
This listingDesign Engineer - STA$109,700 to $175,500
AI Software Engineer$109,700 to $175,500
Senior Digital / Mixed-Signal IC Design or Verification Engineer$109,700 to $175,500
DSP System Architect$109,700 to $175,500
Staff IC Verification Engineer$109,700 to $175,500
Reliability Engineer$109,700 to $175,500
Mainframe Software Development Engineer in Test$109,700 to $175,500
Chart as a table
| Role | Published base |
|---|---|
| Design Engineer - STA (this listing) | $109,700 - $175,500 |
| AI Software Engineer | $109,700 - $175,500 |
| Senior Digital / Mixed-Signal IC Design or Verification Engineer | $109,700 - $175,500 |
| DSP System Architect | $109,700 - $175,500 |
| Staff IC Verification Engineer | $109,700 - $175,500 |
| Reliability Engineer | $109,700 - $175,500 |
| Mainframe Software Development Engineer in Test | $109,700 - $175,500 |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-09-01
Where this pay comes from
Location as the employer wrote it: USA-Colorado-Fort Collins-4380 Ziegler Road
The annual base salary range for this position is USD 109,700.00 To USD 175,500.00
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
