Member of Technical Staff, TPU Kernel Engineering
Company websiteinferact.ai (Inferact, opens in new tab)
Base salary $200K to $400K
Employer-published annual base salary, USD. Advertised base range in San Francisco, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSan Francisco, CA
- WorkplaceOn-site
- Status at last checkSource accepting applications when checked
- Last checked (3 h ago) · observed since
About this job
Inferact's mission is to grow vLLM as the world's AI inference engine and accelerate AI progress by making inference cheaper and faster. Founded by the creators and core maintainers of vLLM, we sit at the intersection of models and hardware, a position that took years to build.
About the Role
We're looking for a TPU kernel engineer to make vLLM a first-class inference engine on Google TPUs. A large part of this role is designing, writing, and optimizing kernels for TPU in Pallas and JAX, for the operations that dominate LLM inference: attention, GEMM, sampling, KV cache, and fused operations.
You'll work at the boundary of kernels, compilers, inference systems, and hardware architecture. You'll profile production-relevant models on TPU, find the bottleneck, and write the kernel or compiler change that removes it, with clear correctness, latency, and throughput benchmarks. Your work will help make TPU support in vLLM usable, fast, benchmarked, and maintainable.
Inferact has three kernel roles. If your kernel work is mostly on Google TPUs (Pallas, JAX), apply to TPU Kernel Engineering. If it is mostly on AMD GPUs (HIP, CK, AITER), apply to AMD GPU Kernel Engineering. For NVIDIA GPUs and cross-platform kernel work, apply to Kernel Engineering. Apply to one; we route you to the best fit.
Skills and Qualifications
Minimum qualifications:
Bachelor's degree or equivalent experience in computer science, engineering, systems, machine learning, or similar.
Hands-on experience designing and implementing kernels for TPUs or other ML accelerators, in Pallas, Triton, CUDA, or a similar kernel language.
Hands-on experience building or optimizing TPU workloads using JAX, XLA, Pallas, or related compiler and runtime tooling.
Deep understanding of TPU execution, memory behavior, compilation, and performance constraints for ML workloads.
Experience optimizing ML kernels such as attention, GEMM, sampling, KV cache, or fused kernels.
Strong performance profiling and benchmarking skills, with the ability to use measurements, compiler artifacts, correctness tests, and reproducible benchmarks to guide optimization work.
Preferred qualifications:
Experience with vLLM, SGLang, TensorRT-LLM, XLA-based serving, or other LLM inference systems.
Familiarity with batching, KV cache, decoding, serving tradeoffs, and backend performance constraints in production inference systems.
Experience with compiler technologies such as XLA, MLIR, LLVM, Pallas, or other kernel DSLs, including lowering, fusion, and backend code generation.
Knowledge of quantization methods such as INT8, FP8, mixed precision, or TPU-specific numeric formats, including accuracy and performance tradeoffs.
Experience building quantitative models of system performance, such as roofline analysis, simulation, or hardware microbenchmarking, and using them to guide kernel work.
Bonus points if you have:
Contributed to vLLM, JAX/XLA, Pallas, PyTorch/XLA, compiler projects, or other open-source ML infrastructure.
Built TPU benchmarking infrastructure or automated performance regression detection for accelerator workloads.
Worked directly with Google TPU ecosystem stakeholders, accelerator platform teams, or early-access programs to ship backend, compiler, or inference performance improvements.
Representative projects
Write a Pallas attention or MoE kernel that beats the current XLA lowering for a production model.
Implement low-latency, high-throughput sampling for large language models on TPU.
Adapt existing models for low-precision inference on TPU.
Debug kernel performance at the compiler-artifact or assembly level.
Logistics
Location: This role is based in San Francisco, California. Will consider remote in the US for exceptional candidates.
Compensation: Depending on background, skills, and experience, the expected annual salary range for this position is $200,000 - $400,000 USD + equity.
Visa sponsorship: We sponsor visas on a case-by-case basis.
Benefits: Inferact offers generous health, dental, and vision benefits as well as 401(k) company match.
Inferact, Inc. is an E-Verify company, and you may review the Notice of E-Verify Participation and the Right to Work posters in English and Spanish.
Source: Inferact on Ashby · View original posting (opens in new tab)
Pay in context
This role's base floor ($200,000) is above 70% of the 5,064 Software Engineering roles in California listed on this site; 199 others list the same floor. Their median floor is $176,800; the middle half runs from $149,391 to $204,000.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 7, 2026.
This listingMember of Technical Staff, TPU Kernel Engineering$200K to $400K
Member of Technical Staff, Performance and Scale$200K to $400K
Engineering Manager$200K to $400K
Member of Technical Staff, Cloud Orchestration$200K to $400K
Member of Technical Staff, AMD GPU Kernel Engineering$200K to $400K
Member of Technical Staff, Forward Deployed Engineer$200K to $400K
Member of Technical Staff, Developer Relations$200K to $400K
Chart as a table
| Role | Published base |
|---|---|
| Member of Technical Staff, TPU Kernel Engineering (this listing) | $200K - $400K |
| Member of Technical Staff, Performance and Scale | $200K - $400K |
| Engineering Manager | $200K - $400K |
| Member of Technical Staff, Cloud Orchestration | $200K - $400K |
| Member of Technical Staff, AMD GPU Kernel Engineering | $200K - $400K |
| Member of Technical Staff, Forward Deployed Engineer | $200K - $400K |
| Member of Technical Staff, Developer Relations | $200K - $400K |
Observed changes
- Began meeting the published-salary criteria
- First observed on the employer's board
- fields changed
- Observed since
- Employer-stated posting date
- 2026-06-17
Where this pay comes from
Location as the employer wrote it: San Francisco
USD 200,000 – 400,000 · 1 YEAR · Salary
- Method
- Structured pay field published by the employer
- Checked
- Rule set
- us-base-v2
The employer's job board publishes this pay as a dedicated data field. We read the field directly; no interpretation was needed.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
