Microarchitecture and Design Engineer - AI SoC
Company websiteintel.com (Intel, opens in new tab)
Base salary From $105,650
Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSanta Clara, CA
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (1 h ago) · observed since
About this job
Job Details:
Job Description:
The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.
Join Intel's AI Revolution Intel's AI SoC organization develops cutting-edge products powering a wide range of AI applications, from edge devices to data center accelerators. If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, you are the ideal candidate for this role. Join us to shape the future of AI hardware.
This role is at the heart of Intel's product development process, combining technical expertise, creative problem-solving, and disciplined execution. By joining our team, you will contribute to the design and development of next-generation technologies that power the future of computing, enabling transformative experiences for billions of users worldwide. This is your opportunity to work alongside some of the brightest minds in the industry, leveraging innovative methodologies to overcome challenging design problems and shaping the future of technology.
Key Responsibilities:
Develop logic design, RTL coding, and simulation for SoC designs.
Define and implement architecture and microarchitecture features for logic blocks.
Perform quality checks across RTL, timing, power, and design integrity to meet performance goals.
Optimize RTL logic to ensure compliance with power, performance, area, and timing targets.
Collaborate with IP providers to integrate and validate IPs at the SoC level.
Review and contribute to verification plans and ensure design features are comprehensively tested.
Identify and resolve RTL test failures to ensure feature correctness.
Employ secure development practices to address security objectives and threats in the design.
Drive quality assurance compliance for seamless IP and SoC handoff throughout the design flow.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.
Minimum Qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 1+ years of hands-on experience in logic design, RTL coding, and simulation, with demonstrated skills gained through internships, academic projects, coursework, or hands-on training OR a Master's degree in Electrical Engineering, Computer Engineering, or related field with no prior professional experience.
Proficiency in RTL coding languages such as Verilog or VHDL.
Familiarity with logic design tools and methodologies for synthesis, timing analysis, and power optimization.
Knowledge of design principles for SoCs and IP integration.
Preferred Qualifications:
Strong analytical and problem-solving skills with a keen eye for detail.
Effective communication and collaboration skills for cross-functional teamwork.
Interest in contributing to secure design practices and quality assurance processes.
Your expertise will support Intel's leadership in innovation and technology. Take the next step in your career journey by applying today.
Job Type:
College GradShift:
Shift 1 (United States of America)Primary Location:
US, California, Santa ClaraAdditional Locations:
US, California, FolsomPosting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust
N/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $105,650.00-172,860.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Source: Intel on Workday · View original posting (opens in new tab)
This listingMicroarchitecture and Design Engineer - AI SoCFrom $105,650
Enterprise Systems AnalystFrom $105,300
Firewall Network Security EngineerFrom $105,300
CPU Physical Design EngineerFrom $105,650
SoC Debug EngineerFrom $105,650
Design Verification EngineerFrom $105,650
Ethernet System Integration EngineerFrom $105,650
Chart as a table
| Role | Published base |
|---|---|
| Microarchitecture and Design Engineer - AI SoC (this listing) | From $105,650 |
| Enterprise Systems Analyst | From $105,300 |
| Firewall Network Security Engineer | From $105,300 |
| CPU Physical Design Engineer | From $105,650 |
| SoC Debug Engineer | From $105,650 |
| Design Verification Engineer | From $105,650 |
| Ethernet System Integration Engineer | From $105,650 |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-11-06
Where this pay comes from
Location as the employer wrote it: US, California, Santa Clara • US, California, Folsom
Annual Salary Range for jobs which could be performed in the US: $105,650.00-172,860.00 USD
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
