Six Figure Work

Senior Circuit Timing Engineer

NVIDIA

Company websitenvidia.com (NVIDIA, opens in new tab)

Base salary $168,000  to $310,500

Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA +1 more

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  • LocationSanta Clara, CA +1 more
  • WorkplaceWorkplace not stated
  • Status at last checkSource accepting applications when checked
  • Last checked (1 h ago) · observed since
All places named
  • Santa Clara, CA
  • California

About this job

We are now looking for a Senior Circuit Timing Engineer!


NVIDIA stands at the intersection of hardware excellence and AI breakthrough, where every line of code and every chip design ripples across industries worldwide. We've built the computational backbone for autonomous systems, revolutionized data center architecture, and created the silicon that powers the AI revolution. Our resilience through decades of technological shifts has forged a unique engineering culture—one where ambitious projects meet exceptional talent. From deep learning frameworks to cutting-edge robotics, we're not just participants in the fourth industrial revolution; we're its architects. Discover how your engineering vision can reshape the world alongside ours.


What you'll be doing:

  • Participate in ground breaking processor design in deep submicron technologies.
  • Work as part of a global circuits team to design innovative circuits for hardware security, adaptive clocking, and power management solutions.
  • Drive timing analysis and signoff of custom circuit macros (digital, semi-custom and analog mixed-signal).
  • Validate timing of custom circuit designs using STA tools including Nanotime, PrimeTime, Tempus and various SPICE simulation tools.
  • Collaborate with cross-functional teams to improve the power, performance, area and reliability of NVIDIA's next generation products through custom circuit solutions and detailed transistor-level analysis.
  • Develop timing models and methodology for innovative and unique custom macro designs.
  • Transistor-level circuit design and timing, schematic entry, and layout delivery.
  • Integrate AI/ML techniques directly into the design process and methodology.
  • Work with PD, DFX, Clocks, and other teams on timing signoff strategy, timing constraints, timing and power convergence, DFT, as well as timing ECO implementation.

What we need to see:

  • BSEE/MS preferred in Electrical, Computer Engineering or equivalent experience.
  • 6+ years of digital circuit design experience for Masters and 8+ years for Bachelors.
  • Excellent understanding of deep submicron process issues and digital circuit design techniques is required.
  • Expertise and in-depth knowledge of industry standard STA tools such as Nanotime, Primetime, Tempus, and other timing analysis tools.
  • Hands on experience running Spice simulations, EM/IR analysis, and static timing analysis/closure is required.
  • Proven experience in timing constraints generation and management.
  • Hands on experience in design and analysis of low power circuits (power gating, decaps, multi-vt, etc..) is a plus.
  • Expertise in analysis and fixing of timing paths through ECOs including crosstalk and glitch noise.
  • Solid understanding of extracted timing models and the usage of .libs in Primetime.
  • Knowledge of process variation effect modeling and experience in design convergence in multi GHz deep submicron technology.

Ways to stand out from the crowd:

  • Proven ownership and hands-on experience across the entire silicon design flow, from micro-architecture and RTL design to back-end execution, including Custom/Semi-Custom Circuit Design, Synthesis, Auto Place and Route, STA, and PVerf.
  • Proven capability in Post-Silicon characterization and debug, ensuring designs meet performance targets in hardware.
  • Track record of independently driving and delivering complex features from conception through tape-out and validation.
  • Knowledge of timing closure strategies for digital logic/macros part of AMS designs/IPs.
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:
168,000 USD – 264,500 USD for Level 4; and 196,000 USD – 310,500 USD for Level 5.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 3, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Source: NVIDIA on Workday · View original posting (opens in new tab)

This range next to 6 other live NVIDIA roles with the nearest advertised base floor
Chart as a table
This range next to 6 other live NVIDIA roles with the nearest advertised base floor
RolePublished base
Senior Circuit Timing Engineer (this listing)$168,000 - $310,500
L11 System Product Development Engineer$168,000 - $258,750
Senior Software Engineer, Network Visibility Platform - DGX Cloud$168K - $322K
Hardware Validation Procedures and Documentation Lead$168,000 - $258,750
Senior Software Engineer, Platform Engineering$168K - $322K
AI Engineering Manager - Finance$168K - $322K
Senior Technical Program Manager – DFX Software Methodology$168K - $322K

Same $100K to $400K scale as every card. All NVIDIA roles · How to read the bar

Observed changes

  1. First observed on the employer's board
  2. Began meeting the published-salary criteria
Observed since
Employer-stated posting date
2026-10-30
Where this pay comes from

Location as the employer wrote it: US, CA, Santa Clara • US, CA, Remote (Levels 4-5 combined)

168,000 USD – 264,500 USD for Level 4; and 196,000 USD – 310,500 USD for Level 5.

Method
Employer text, read with fixed rules and re-verified
Checked
Rule set
us-base-v2

The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.

What we verified

  • The pay figures come from the employer's own listing, quoted exactly above.
  • The pay is an annual base salary in US dollars with a minimum of at least $100,000.
  • The role was publicly listed on the employer's job board when last checked.

We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.