ASIC Design Engineer - Hardware

Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies and delivering system-level IP to measure performance across multiple projects!

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world!

What you'll be doing:

• Be an integral part of the team defining, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs

• Define, develop, and automate flows and methodologies to efficiently build, deliver, and support a system-level IP

• Deliver IP and support projects by applying the performance monitoring system

• Run and debug RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset, latency, and more)

• Design and implement RTL features (microarchitecture and RTL)

• Work with architects, designers, and software engineers to accomplish your tasks

What we need to see:

• BS or equivalent experience in Electrical Engineering, Computer Engineer, or related degree required, advanced degrees (MS, PhD) a plus

• 2+ years of relevant industry experience and strong coding skills in Perl/Python or other industry-standard scripting languages

• Experience in RTL design (Verilog), verification (SystemVerilog), System-On-Chip design/implementation flow, and design automation

• Good understanding of SOC architecture, including CDC, multiple-power domains, performance analysis, latency, and data flow

• Excellent debugging and analytical skills

• Exposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Debussy, GDB)

• Great communication and collaboration skills to interact within the team and with cross-functional teams

Ways to stand out from the crowd:

• Hands on experience in object-oriented programming

• Prior design on system level IP (Clocks/DFT/Resets)

• Experience developing methodologies used by others

• Hands- on silicon debug is a plus.

• Exposure to physical design

With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant people in the world working for us and, due to unprecedented growth, our teams are rapidly growing. Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology? If so, we want to hear from you.

#LI-Hybrid

Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:
116,000 USD – 189,750 USD for Level 2; and 136,000 USD – 218,500 USD for Level 3.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 3, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.