Six Figure Work

ASIC Package Design Engineer

Broadcom

Company websitebroadcom.com (Broadcom, opens in new tab)

Base salary $143,800  to $230,000

Employer-published annual base salary, USD. Advertised base range in San Jose Innovation Drive, CA +2 more

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  • LocationSan Jose Innovation Drive, CA +2 more
  • WorkplaceWorkplace not stated
  • Status at last checkSource accepting applications when checked
  • Last checked (1 h ago) · observed since
All places named
  • San Jose Innovation Drive, CA
  • USA-TX-Austin - River Place B7
  • USA-Colorado-Fort Collins-4380 Ziegler Road

About this job

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Job Description:

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs. You will be part of a worldwide R&D team developing high-performance package designs for ASICs for artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations. These designs include SerDes at 448G and higher, 5G RF/Microwave ADC/DAC, HBM, DDR5 and more. You'll have the opportunity to collaborate with the team to create the package structures needed to enable new design, and contribute to efficiency improvements for our design team.

RESPONSIBILITIES:

  • Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.
  • Package Design of critical structures for SerDes, ADC/DAC, DDR, HBM, etc.
  • Schedule, prioritize, and track your work across 2+ projects simultaneously
  • General flip-chip BGA package design and engineering
  • Project management and customer interface for your design projects
  • Contribute to efficiency improvements for the design team, through process development/improvement, automation, documentation, etc.
  • Physical design (layout) is a foundational responsibility in this role

 
EDUCATION/EXPERIENCE & REQUIREMENTS:

  • BSEE or similar field and 12+ years’ experience in flip-chip-BGA package design, including high-speed SerDes or MSEE or similar field and 10+ years’ work experience
  • Knowledge of package-level signal integrity and power integrity, to apply to package designs
  • Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.
  • Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers
  • Self-management and organization skills
  • Preferred candidates will also have 1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest

OTHER REQUIREMENTS

  • This job requires working on-site at the Broadcom office, 5 days a week. This is not a remote-work position.

Compensation and Benefits


The annual base salary range for this position is USD 143,800.00 To USD 230,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.


Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.


Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.


If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Source: Broadcom on Workday · View original posting (opens in new tab)

This range next to 6 other live Broadcom roles with the nearest advertised base floor
Chart as a table
This range next to 6 other live Broadcom roles with the nearest advertised base floor
RolePublished base
ASIC Package Design Engineer (this listing)$143,800 - $230,000
R&D Engineer IC Design 5$143,800 - $230,000
DFT Lead Engineer$143,800 - $230,000
Principal Physical Design Engineer$143,800 - $230,000
Staff Software Engineer$143,800 - $230,000
R&D Engineer Software 5$143,800 - $230,000
Physical Design Engineer$143,800 - $230,000

Same $100K to $400K scale as every card. All Broadcom roles · How to read the bar

Observed changes

  1. First observed on the employer's board
  2. Began meeting the published-salary criteria
Observed since
Employer-stated posting date
2026-10-19
Where this pay comes from

Location as the employer wrote it: USA-CA San Jose Innovation Drive • USA-TX-Austin - River Place B7 • USA-Colorado-Fort Collins-4380 Ziegler Road

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00

Method
Employer text, read with fixed rules and re-verified
Checked
Rule set
us-base-v2

The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.

What we verified

  • The pay figures come from the employer's own listing, quoted exactly above.
  • The pay is an annual base salary in US dollars with a minimum of at least $100,000.
  • The role was publicly listed on the employer's job board when last checked.

We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.