ASIC Physical Design Engineer, Netlisting - New College Grad 2026
Company websitenvidia.com (NVIDIA, opens in new tab)
Base salary $116,000 to $218,500
Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA +1 more
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSanta Clara, CA +1 more
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (5 min ago) · observed since
All places named
- Santa Clara, CA
- Austin, TX
About this job
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
We are now looking for a motivated ASIC Physical Design Engineer, Netlisting to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, join us today! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing! More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to tackle, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.
What you'll be doing:
Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.
Help in ECO generation and implementation.
What we need to see:
Master's or PhD degree in Electrical or Computer Engineering (or equivalent experience).
Shown knowledge in logic equivalence checking/Formal Verification required from RTL to tapeout with industry-standard tools.
Understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.
Experience in clock-domain-crossing checking, MTBF analysis, either with EDA tools (i.e., Synopsys or Cadence) or in-house tools.
Background with logic synthesis at either block or full-chip level, at project execution and/or flow development.
In-depth knowledge of industry standard EDA tools in related fields.
Experience in programming and scripting languages, such as, Perl, TCL, Make, Python, etc.
Ways to stand out from the crowd:
Experience in logic synthesis and equivalence checking/FV. Familiarity with industry tools and flow.
Strong hands-on debugging capability and problem-solving skills.
Experience improving workflows and productivity through effective AI utilization is a plus.
NVIDIA is widely considered to be the leader of AI computing, and one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:116,000 USD – 189,750 USD for Level 2; and 136,000 USD – 218,500 USD for Level 3.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.Source: NVIDIA on Workday · View original posting (opens in new tab)
Pay in context
This role's base floor ($116,000) is above 15% of the 3,579 Engineering (non-software) roles in California listed on this site; 24 others list the same floor. Their median floor is $147,000; the middle half runs from $125,000 to $173,000.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 8, 2026.
This listingASIC Physical Design Engineer, Netlisting - New College Grad 2026$116,000 to $218,500
Global Virtual Card Payment Administrator$116,000 to $195,500
Forward Deployed Engineer - Finance$116K to $230K
Customer Solutions Architect, Applications Engineering$116,000 to $189,750
Senior Revenue Accountant – Revenue Accounting Operations$116,000 to $195,500
ASIC Design Engineer – Clocks IP$116,000 to $218,500
Deep Learning Compiler Verification Engineer$116,000 to $189,750
Chart as a table
| Role | Published base |
|---|---|
| ASIC Physical Design Engineer, Netlisting - New College Grad 2026 (this listing) | $116,000 - $218,500 |
| Global Virtual Card Payment Administrator | $116,000 - $195,500 |
| Forward Deployed Engineer - Finance | $116K - $230K |
| Customer Solutions Architect, Applications Engineering | $116,000 - $189,750 |
| Senior Revenue Accountant – Revenue Accounting Operations | $116,000 - $195,500 |
| ASIC Design Engineer – Clocks IP | $116,000 - $218,500 |
| Deep Learning Compiler Verification Engineer | $116,000 - $189,750 |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-10-30
Where this pay comes from
Location as the employer wrote it: US, CA, Santa Clara • US, TX, Austin (Levels 2-3 combined)
116,000 USD – 189,750 USD for Level 2; and 136,000 USD – 218,500 USD for Level 3.
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
