Six Figure Work

Digital IC Design Engineer

Neuralink

Company websiteneuralink.com (Neuralink, opens in new tab)

Base salary $116,000  to $233,800

Employer-published annual base salary, USD. Advertised base range in Austin, TX +1 more

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  • LocationAustin, TX +1 more
  • WorkplaceWorkplace not stated
  • Status at last checkSource accepting applications when checked
  • Last checked (3 h ago) · observed since
All places named
  • Austin, TX
  • South San Francisco, CA

About this job

About Neuralink:

We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.

Team Description: 

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. 

Job Description & Responsibilities: 

Our Digital IC Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred.

  • Micro-architecture design and RTL implementation of: 
    • Low-power digital signal processors
    • Low-power general-purpose hardware accelerators
    • Low-power graphics processing units
    • Low-power radio MAC/PHY
    • Low-power serial link MAC/PHY
  • Design and optimization of hardware/software interface with firmware engineers
  • Application-specific architecture optimization including:
    • Complex system modeling for energy and performance benchmarks
    • Workload analysis and modeling
    • Energy/performance profiling and analysis
    • Leveraging architecture-level design trade-offs with process technology and workload type
    • Balancing cost and performance under manufacturing process variation 
  • Collaboration on silicon bring-up tests with verification engineers 

Required Qualifications:

  • Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience
  • Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
  • 5+ years of experience in digital design
  • Expertise in SystemVerilog, C/C++, Python
  • Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
  • Experience in designing digital signal processing pipelines, from algorithm to RTL

Preferred Qualifications: 

  • Experience in architecture optimization with process technology customization
  • Experience in the verification of complex digital systems, using industry standard tools
  • Experience in the physical design of complex digital systems, using industry standard tools
  • Experience testing and debugging digital system-on-a-chips
  • Functional modeling experience and logic verification with SystemVerilog, SystemC/C++
  • Experience automating tool flows
  • Experience with embedded design
  • Experience in processor instruction set architecture design
  • Experience in compiler back-end design and customization

Expected Compensation:

The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees’ success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees.

Base Salary Range:

$116,000—$233,800 USD

What We Offer:

Full-time employees are eligible for the following benefits listed below.

  • An opportunity to change the world and work with some of the smartest and most talented experts from different fields
  • Growth potential; we rapidly advance team members who have an outsized impact
  • Excellent medical, dental, and vision insurance through a PPO plan
  • Paid holidays
  • Commuter benefits
  • Meals provided
  • Equity (RSUs) *Temporary Employees & Interns excluded
  • 401(k) plan *Interns initially excluded until they work 1,000 hours
  • Parental leave *Temporary Employees & Interns excluded
  • Flexible time off *Temporary Employees & Interns excluded

Source: Neuralink on Greenhouse · View original posting (opens in new tab)

Pay in context

This role's base floor ($116,000) is above 25% of the 173 Engineering (non-software) roles in Texas listed on this site; 3 others list the same floor. Their median floor is $136,600; the middle half runs from $115,527 to $159,200.

Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 6, 2026.

This range next to 6 other live Neuralink roles with the nearest advertised base floor
Chart as a table
This range next to 6 other live Neuralink roles with the nearest advertised base floor
RolePublished base
Digital IC Design Engineer (this listing)$116,000 - $233,800
Software Engineer, Robotics$119K - $200K
Embedded Software Engineer, Implant Embedded Systems$119K - $281K
Software Engineer, Implant$119K - $200K
Software Engineer, Medical Imaging$113K - $188K
Materials Engineer$113K - $209K
Mechanical Engineer, Implant$120K - $224K

Same $100K to $400K scale as every card. All Neuralink roles · How to read the bar

Observed changes

  1. First observed on the employer's board
  2. Began meeting the published-salary criteria
Observed since
Employer-stated posting date
2023-06-27
Where this pay comes from

Location as the employer wrote it: Austin, Texas, United States; South San Francisco, California, United States

$116,000—$233,800 USD

Method
Employer text, read with fixed rules and re-verified
Checked
Rule set
us-base-v2

The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.

What we verified

  • The pay figures come from the employer's own listing, quoted exactly above.
  • The pay is an annual base salary in US dollars with a minimum of at least $100,000.
  • The role was publicly listed on the employer's job board when last checked.

We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.