Digital Verification Engineer
Company websiteneuralink.com (Neuralink, opens in new tab)
Base salary $131K to $243K
Employer-published annual base salary, USD. Advertised base range in South San Francisco, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSouth San Francisco, CA
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (2 h ago) · observed since
About this job
About Neuralink:
We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.
Job Description & Responsibilities:
We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification fundamentals to work in Neuralink’s System-on-Chip (SoC) department under the Implant Team. This position offers a rare and unique opportunity to have a high impact in realizing state-of-the-art brain-computer interfaces. The team delivers architecture and logic implementation of digital modules with a strong focus in high-throughput low-power digital signal processing (DSP) . We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.
Required qualifications:
- Minimum 3 years of experience in digital ASIC verification.
- Excellence in SystemVerilog.
- Experience in developing automation flow and scripts such as Python, Perl, Makefile, Tcl and UNIX shell
- Experience with code coverage and regression setup.
- Bachelor's degree in a technical field OR equivalent experience.
Preferred qualifications:
- Experience working on complex digital systems from architecture, microarchitecture, RTL, verification and physical design using industry standard tools.
- Experience on building test benches, testing, and debugging for a complex system-on-chip.
- Experience in formal verification.
- Functional modeling experience and logic verification with SystemVerilog, SystemC/C++.
- Experience with IEEE-1801 (UPF) based design simulation flows
- Experience with low power gate level simulations
- Exposure with low power formal verification flows
- Strong hands-on experience in verification methodologies such as UVM
- Knowledge of ARM/RISC-V processor, AMBA bus
- Knowledge of power aware verification
- Experience with FPGA/emulation
- Experience with lab system bring up, writing diagnostic, and lab debugging
Expected Compensation:
The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees’ success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees.
Base Salary Range:
$131,000—$243,000 USD
What We Offer:
Full-time employees are eligible for the following benefits listed below.
- An opportunity to change the world and work with some of the smartest and most talented experts from different fields
- Growth potential; we rapidly advance team members who have an outsized impact
- Excellent medical, dental, and vision insurance through a PPO plan
- Paid holidays
- Commuter benefits
- Meals provided
- Equity (RSUs) *Temporary Employees & Interns excluded
- 401(k) plan *Interns initially excluded until they work 1,000 hours
- Parental leave *Temporary Employees & Interns excluded
- Flexible time off *Temporary Employees & Interns excluded
Source: Neuralink on Greenhouse · View original posting (opens in new tab)
Pay in context
This role's base floor ($131,000) is above 31% of the 2,072 Engineering (non-software) roles in California listed on this site; 1 other lists the same floor. Their median floor is $146,500; the middle half runs from $125,000 to $175,000.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 6, 2026.
This listingDigital Verification Engineer$131K to $243K
Physical Design and Verification Engineer$131K to $265K
Machine Learning Engineer$129K to $331K
Software Engineer, BCI Applications$128K to $281K
Software Engineer, Robot Manufacturing$135K to $216K
UI Design Engineer$135K to $281K
Software Engineer, Pathology and Digital Imaging$135K to $216K
Chart as a table
| Role | Published base |
|---|---|
| Digital Verification Engineer (this listing) | $131K - $243K |
| Physical Design and Verification Engineer | $131K - $265K |
| Machine Learning Engineer | $129K - $331K |
| Software Engineer, BCI Applications | $128K - $281K |
| Software Engineer, Robot Manufacturing | $135K - $216K |
| UI Design Engineer | $135K - $281K |
| Software Engineer, Pathology and Digital Imaging | $135K - $216K |
Observed changes
- Began meeting the published-salary criteria
- First observed on the employer's board
- Observed since
- Employer-stated posting date
- 2026-08-04
Where this pay comes from
Location as the employer wrote it: South San Francisco, California, United States
USD 131,000 – 243,000 · interval unstated · pay_input_range · Base Salary Range: · base-labelled (R1: Base Salary)
- Method
- Structured pay field published by the employer
- Checked
- Rule set
- us-base-v2
The employer's job board publishes this pay as a dedicated data field. We read the field directly; no interpretation was needed.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
