Six Figure Work

Director - Intel Foundry Pre-Silicon Design Quality and Reliability

Intel

Company websiteintel.com (Intel, opens in new tab)

Base salary From $271,620

Employer-published annual base salary, USD. Advertised base range in Hillsboro, OR

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  • LocationHillsboro, OR
  • WorkplaceWorkplace not stated
  • Status at last checkSource accepting applications when checked
  • Last checked (38 min ago) · observed since

About this job

Job Details:

Job Description: 

The Role and Impact
As the leader of Intel's Foundry pre-Silicon Quality and Reliability team, you will lead a high-performing team of Design and Quality and Reliability engineers responsible for the tools and flows which allow Foundry customers to design reliable, high performance products on Intel Silicon technologies. You will play a key role in shaping and implementing best-in-class engineering practices, delivering impactful results, and contributing to Intel's success in achieving its strategic goals. This position offers a unique opportunity to influence the future of Intel's technology and business success by fostering a culture of customer orientation, innovation, collaboration, and continuous improvement.

Key Responsibilities

  • Lead Intel's Q and R Pre-Siilcon Design team to develop and deploy world-class methodologies, tools and flows enabling customers to achieve their reliability requirements on Intel technologies
  • Mentor and develop a team of design and quality and reliability engineers and build disciplined collaboration structures with internal and external partners, promoting a collaborative, inclusive, and productive work environment that aligns with Intel's values.
  • Develop innovative solutions to enable customers to achieve design quality and reliability and fully exploit the capabilities of Intel's technologies..
  • Partner with cross-functional teams to align tools and methods with internally and consistent with expectations of the customer ecosystem
  • Implement and monitor key performance metrics to ensure quality, efficiency, and alignment with business objectives.

Required Skills and Experience

  • Proven expertise in use of Reliability Design tools on leading edge products and Designs
  • Strong technical background in Design engineering, architecture, and lifecycle management.
  • Demonstrated ability to lead and manage teams, with a track record of achieving team goals and driving results.
  • Proficiency in performance metrics analysis and application of root cause methodologies.
  • Experience in customer and EDA engagements and delivering high-quality solutions aligned with business needs.

Preferred Skills and Experience

  • Experience in managing multi-level, cross-site, and global engineering teams.
  • Exceptional communication skills, both written and verbal, with the ability to influence and collaborate across various organizational levels.
  • Strategic mindset with the ability to propose and implement long-term improvements and innovative solutions.
  • Knowledge of semiconductor design, validation, and process modeling.
  • Passion for building inclusive teams and fostering a culture of engagement and continuous development.

Qualifications:

  • Bachelor's degree Electrical Engineering, or a related field, or equivalent work experience. Master's or PhD preferred,
  • 12+ years of experience with a Bachelor's degree, 8+ years with a Master's degree, or 6+ years with a PhD in software development, engineering, or a related domain.
  • Extensive experience in leading quality and reliability

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Oregon, Hillsboro

Additional Locations:

US, California, Santa Clara

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $271,620.00-383,460.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Source: Intel on Workday · View original posting (opens in new tab)

Pay in context

This role's base floor ($271,620) is above 99% of the 155 Engineering (non-software) roles in Oregon listed on this site. Their median floor is $129,200; the middle half runs from $116,800 to $148,450.

Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 8, 2026.

This range next to 6 other live Intel roles with the nearest advertised base floor
Chart as a table
This range next to 6 other live Intel roles with the nearest advertised base floor
RolePublished base
Director - Intel Foundry Pre-Silicon Design Quality and Reliability (this listing)From $271,620
Senior Principal Engineer, Device DesignFrom $265,480
Sr. Director, Networking Hardware Product ManagementFrom $257,740
Sr Director, XSE Design Verification EngineeringFrom $256,050
Physical AI Solutions ArchitectFrom $255,850
Principal Engineer, AI Applied ResearchFrom $255,850
GPU Software EngineerFrom $255,850

Same $100K to $400K scale as every card. All Intel roles · How to read the bar

Observed changes

  1. First observed on the employer's board
  2. Began meeting the published-salary criteria
Observed since
Employer-stated posting date
2026-07-22
Where this pay comes from

Location as the employer wrote it: US, Oregon, Hillsboro • US, California, Santa Clara

Annual Salary Range for jobs which could be performed in the US: $271,620.00-383,460.00 USD

Method
Employer text, read with fixed rules and re-verified
Checked
Rule set
us-base-v2

The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.

What we verified

  • The pay figures come from the employer's own listing, quoted exactly above.
  • The pay is an annual base salary in US dollars with a minimum of at least $100,000.
  • The role was publicly listed on the employer's job board when last checked.

We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.

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