EDA Tools Hardware Engineer
Company websiteintel.com (Intel, opens in new tab)
Base salary From $141,910
Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSanta Clara, CA
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (26 min ago) · observed since
All 4 locations
- US, California, Santa Clara
- US, Oregon, Hillsboro
- US, California, Folsom
- US, Texas, Austin
About this job
Job Details:
Job Description:
The Role and Impact
Join Intel's world-class team as an EDA Tools Hardware Engineer, where you will play a pivotal role in shaping the future of silicon innovation. This position directly contributes to the enablement and adoption of cutting-edge hardware design tools, flows, and methodologies. Your work will enhance the efficiency of design processes and optimize power, performance, and technology node advancements. As part of Intel, you will have the unique opportunity to collaborate with EDA vendors, define next-generation design tools, and contribute to groundbreaking innovations that enrich lives worldwide.
Key Responsibilities
Full Chip Implementation Flow Development
Develop and maintain full-chip physical implementation flows including:
Floor planning and partitioning strategies
Hierarchical block integration
Chip-level placement and routing coordination
Power grid planning and analysis
Clock tree synthesis (CTS) strategy integration
Enable scalable SoC assembly flows for multi-block and multi-power domain designs.
Define methodology for hierarchical design reuse and integration
Qualifications:
Minimum Qualifications
Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field with 6+ years of experience; or a Master's degree with 4+ years of experience; or a PhD with 2+ years of experience
Physical design fundamentals (I.e. placement, routing)
Clock tree synthesis (CTS)
Full-chip integration methodologies using Innovus
Preferred Qualifications
Static timing analysis (STA)
Power grid design and IR drop concepts
Experience with large SoC or multi-block design implementation flows
Experience scripting and automation skills in Linux environments
Job Type:
Experienced HireShift:
Shift 1 (United States of America)Primary Location:
US, California, Santa ClaraAdditional Locations:
US, California, Folsom, US, Oregon, Hillsboro, US, Texas, AustinPosting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust
N/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Source: Intel on Workday · View original posting (opens in new tab)
Pay in context
This role's base floor ($141,910) is above 44% of the 2,077 Engineering (non-software) roles in California listed on this site; 4 others list the same floor. Their median floor is $146,200; the middle half runs from $125,000 to $175,000.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 6, 2026.
This listingEDA Tools Hardware EngineerFrom $141,910
Product Development/DFX Lead - Neuromorphic ComputingFrom $141,910
GPU Design Verification EngineerFrom $141,910
AI Silicon Performance Modeling and Analysis EngineerFrom $141,910
Quantum Computing Measurement EngineerFrom $141,910
Design Verification EngineerFrom $141,910
GPU Logic Design EngineerFrom $141,910
Chart as a table
| Role | Published base |
|---|---|
| EDA Tools Hardware Engineer (this listing) | From $141,910 |
| Product Development/DFX Lead - Neuromorphic Computing | From $141,910 |
| GPU Design Verification Engineer | From $141,910 |
| AI Silicon Performance Modeling and Analysis Engineer | From $141,910 |
| Quantum Computing Measurement Engineer | From $141,910 |
| Design Verification Engineer | From $141,910 |
| GPU Logic Design Engineer | From $141,910 |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-10-02
Where this pay comes from
Location as the employer wrote it: Multiple locations (4)
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
