Lead Systems Signal Integrity/Power Integrity Engineer
Company websitecerebras.ai (Cerebras, opens in new tab)
Base salary $220K to $250K
Employer-published annual base salary, USD. Advertised base range in Sunnyvale, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSunnyvale, CA
- WorkplaceOn-site
- Status at last checkSource accepting applications when checked
- Last checked (22 min ago) · observed since
About this job
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.
This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.
Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.
We are seeking an experienced System Signal Integrity and Power Integrity Engineer Lead to solve complex, high‑impact integrity challenges in next‑generation AI compute systems. This role is focused on deep technical analysis and hands‑on problem solving across high‑speed interfaces, power delivery networks, rigid and flex interconnects, and advanced packaging.
The ideal candidate is a technical expert engaged to resolve difficult SI/PI problems spanning silicon, package, PCB, flex, and connector domains.
Key Responsibilities:
- Solve complex signal integrity and power integrity problems for high‑speed AI compute platforms, including chip‑to‑chip and chip‑to‑board interfaces.
- Perform advanced pre‑layout and post‑layout SI/PI analysis across PCBs, flex circuits, rigid‑flex assemblies, connectors, and advanced packages.
- Lead root‑cause analysis of challenging SI/PI issues such as margin shortfalls, impedance discontinuities, coupling, resonances, and simulation‑to‑hardware mismatches.
- Analyze and resolve SI/PI challenges associated with flex circuits, high‑speed flex connectors, interposers, and advanced packaging technologies.
- Analyze and troubleshoot power delivery networks using DC and AC simulations and hardware correlation to resolve performance and stability issues.
- Define and refine PCB, rigid‑flex, and flex circuit stack‑ups, material selections, and impedance structures as required to meet performance targets.
- Review schematics, PCB layouts, and flex designs to identify SI/PI risks and recommend targeted design changes.
- Work closely with silicon and package design teams to resolve SI/PI issues related to bump/ball assignments, package‑to‑PCB transitions, and interface interactions.
- Act as a technical escalation point for complex SI/PI issues across multiple programs.
Minimum Qualifications:
- Master’s degree in Electrical Engineering.
- 15+ years of demonstrated depth of expertise in system-level signal integrity and power integrity engineering for high‑speed hardware systems.
Required Experience and Skills:
- Deep expertise in high‑speed serial and parallel interface analysis and debug.
- Strong hands‑on experience with PCB, rigid‑flex, and flex circuit stack‑up design and analysis.
- Advanced SI/PI analysis of flex connectors, high‑density interconnects, and advanced packaging technologies.
- Proficiency with 2D and 3D electromagnetic simulation tools.
- Power delivery network analysis, simulation, and lab correlation at the system level.
- Strong grounding in transmission line theory, microwave engineering, and high‑speed design fundamentals.
- Proven ability to correlate simulation results with hardware behavior and drive concrete design fixes.
-Experience working on server hardware, AI accelerators, hardware accelerator, datacenter, AI Hardware, enterprise product, GPU, CPU, TPU, server platform etc.
Additional Information:
- Experience with large‑scale AI or high-performance compute systems is preferred.
Location: Sunnyvale, CA
The base salary range for this position is $220,000 to $250,000+ annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.
Why Join Cerebras
People who are serious about software make their own hardware. At Cerebras, we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we’ve reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras:
Build a breakthrough AI platform beyond the constraints of the GPU.
Publish and open source their cutting-edge AI research.
Work on one of the fastest AI supercomputers in the world.
Enjoy job stability with startup vitality.
Our simple, non-corporate work culture that respects individual beliefs.
Find out more about what it's like to work at Cerebras here!
Apply today and become part of the forefront of groundbreaking advancements in AI!
Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.
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Source: Cerebras on Ashby · View original posting (opens in new tab)
Pay in context
This role's base floor ($220,000) is above 91% of the 2,097 Engineering (non-software) roles in California listed on this site; 18 others list the same floor. Their median floor is $146,200; the middle half runs from $124,000 to $174,000.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 7, 2026.
This listingLead Systems Signal Integrity/Power Integrity Engineer$220K to $250K
Staff Design Verification Engineer$225K to $270K
Senior ASIC RTL Design Engineer, AI Hardware$200K to $290K
Lead RTL Design Engineer$200K to $299K
Senior Staff Design Verification Engineer$250K to $300K
Design Verification Engineer$190K to $230K
Systems Debug Engineer- EE$190K to $230K
Chart as a table
| Role | Published base |
|---|---|
| Lead Systems Signal Integrity/Power Integrity Engineer (this listing) | $220K - $250K |
| Staff Design Verification Engineer | $225K - $270K |
| Senior ASIC RTL Design Engineer, AI Hardware | $200K - $290K |
| Lead RTL Design Engineer | $200K - $299K |
| Senior Staff Design Verification Engineer | $250K - $300K |
| Design Verification Engineer | $190K - $230K |
| Systems Debug Engineer- EE | $190K - $230K |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-09-03
Where this pay comes from
Location as the employer wrote it: Sunnyvale, CA
The base salary range for this position is $220,000 to $250,000+ annually. Actual compensation may include bonus and equity
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
