Lead RTL Design Engineer
Company websitecerebras.ai (Cerebras, opens in new tab)
Base salary $200K to $299K
Employer-published annual base salary, USD. Advertised base range in Sunnyvale, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSunnyvale, CA
- WorkplaceOn-site
- Status at last checkSource accepting applications when checked
- Last checked (3 h ago) · observed since
About this job
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.
This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.
Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.
About The Role
As a lead front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE).
This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient, and scalable solutions. The role also requires close collaboration and management of external ASIC vendor. You will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems.
Responsibilities
Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
Managing external ASIC vendor through product development cycle.
Work closely with PD team members for design closure to meet PPA goals.
Work closely with Design verification and DFT teams for achieving the best functional and test coverage.
Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.
Debug silicon-level functional, timing, and power issues during bring up.
Requirements
Master’s degree in Computer Science, Electrical Engineering, or equivalent.
Can work in a hybrid work environment.
8-15 years of experience in delivering complex, high performance high quality RTL designs.
Experience with Front End Chip integration and third-party IP integration.
Demonstrated experience in networking, high-performance computing, machine learning or related fields.
Proven track record of multiple silicon success.
Experience collaborating and managing external vendors.
Experience with designing/integrating high speed IO.
Networking stack experience including TCP/IP, RDMA and Ethernet.
Knowledge of PCIe, CPU interfaces and Serdes technology.
Working knowledge of scripting tools : Python, TCL.
Assets
Experience with FPGA development toolchain, including Place and Route, Floor planning and Timing Analysis is a plus.
The base salary range for this position is $200,000 to $299,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.
Why Join Cerebras
People who are serious about software make their own hardware. At Cerebras, we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we’ve reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras:
Build a breakthrough AI platform beyond the constraints of the GPU.
Publish and open source their cutting-edge AI research.
Work on one of the fastest AI supercomputers in the world.
Enjoy job stability with startup vitality.
Our simple, non-corporate work culture that respects individual beliefs.
Find out more about what it's like to work at Cerebras here!
Apply today and become part of the forefront of groundbreaking advancements in AI!
Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.
This website or its third-party tools process personal data. For more details, click here to review our CCPA disclosure notice.
Source: Cerebras on Ashby · View original posting (opens in new tab)
Pay in context
This role's base floor ($200,000) is above 86% of the 2,034 Engineering (non-software) roles in California listed on this site; 29 others list the same floor. Their median floor is $146,200; the middle half runs from $124,193 to $173,000.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 6, 2026.
This listingLead RTL Design Engineer$200K to $299K
Senior ASIC RTL Design Engineer, AI Hardware$200K to $290K
Design Verification Engineer$190K to $230K
Systems Debug Engineer- EE$190K to $230K
Lead Systems Signal Integrity/Power Integrity Engineer$220K to $250K
Power Manufacturing Test Development Engineer$180K to $220K
Staff Systems Technical Program Manager (Hardware)$180K to $230K
Chart as a table
| Role | Published base |
|---|---|
| Lead RTL Design Engineer (this listing) | $200K - $299K |
| Senior ASIC RTL Design Engineer, AI Hardware | $200K - $290K |
| Design Verification Engineer | $190K - $230K |
| Systems Debug Engineer- EE | $190K - $230K |
| Lead Systems Signal Integrity/Power Integrity Engineer | $220K - $250K |
| Power Manufacturing Test Development Engineer | $180K - $220K |
| Staff Systems Technical Program Manager (Hardware) | $180K - $230K |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-08-07
Where this pay comes from
Location as the employer wrote it: Sunnyvale, CA
The base salary range for this position is $200,000 to $299,000 annually. Actual compensation may include bonus and equity,
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
