Memory System Designer and Place and Route Engineer
Company websitebroadcom.com (Broadcom, opens in new tab)
Base salary $109,700 to $175,500
Employer-published annual base salary, USD. Advertised base range in United States
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationUnited States
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (21 min ago) · observed since
About this job
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Job Description:
We are looking for an energetic and passionate design engineer to join our Central Engineering Group and be part of a memory subsystem design team responsible for the development of large memory blocks and subsystems. Typically requires a minimum of 8 years of relevant experience and a Bachelor in Electrical Engineering.
Job Responsibilities
- Architect and design memory subsystems
- Implement RTL of subsystem designs
- Place and route (physical design)
- Design closure: timing, DRC, LVS, EM/IR, etc.
- Gate netlist synthesis
Skill Set Required
- Strong design skills
- Ability to write and debug Verilog RTL code
- Place and route expertise
- Proficient in running STA, DRC, EM/IR tools, and attaining design closure
- Ability to code in Python
- Good understanding of synthesis tools and running synthesis
- Capable of running and debugging logical equivalency checkers
- Familiar with memory behavior
- Proficient in writing automation scripts, and tools savvy
- Good communication, interpersonal, and leadership skills
- Motivated, self-driven, and good at multitasking
Compensation and Benefits
The annual base salary range for this position is USD 109,700.00 To USD 175,500.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Source: Broadcom on Workday · View original posting (opens in new tab)
Pay in context
This role's base floor ($109,700) is above 6% of the 860 Design roles nationwide listed on this site; 1 other lists the same floor. Their median floor is $155,492; the middle half runs from $132,000 to $183,000.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 7, 2026.
This listingMemory System Designer and Place and Route Engineer$109,700 to $175,500
AI Software Engineer$109,700 to $175,500
Senior Digital / Mixed-Signal IC Design or Verification Engineer$109,700 to $175,500
DSP System Architect$109,700 to $175,500
Staff IC Verification Engineer$109,700 to $175,500
Reliability Engineer$109,700 to $175,500
Mainframe Software Development Engineer in Test$109,700 to $175,500
Chart as a table
| Role | Published base |
|---|---|
| Memory System Designer and Place and Route Engineer (this listing) | $109,700 - $175,500 |
| AI Software Engineer | $109,700 - $175,500 |
| Senior Digital / Mixed-Signal IC Design or Verification Engineer | $109,700 - $175,500 |
| DSP System Architect | $109,700 - $175,500 |
| Staff IC Verification Engineer | $109,700 - $175,500 |
| Reliability Engineer | $109,700 - $175,500 |
| Mainframe Software Development Engineer in Test | $109,700 - $175,500 |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-10-06
Where this pay comes from
Location as the employer wrote it: USA-Mendota Heights-Northland
The annual base salary range for this position is USD 109,700.00 To USD 175,500.00
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
