Mixed Signal Digital Design Lead
Company websitebroadcom.com (Broadcom, opens in new tab)
Base salary $121,900 to $195,000
Employer-published annual base salary, USD. Advertised base range in San Jose Innovation Drive, CA +1 more
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSan Jose Innovation Drive, CA +1 more
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (1 h ago) · observed since
All places named
- San Jose Innovation Drive, CA
- USA-Colorado-Fort Collins-4380 Ziegler Road
About this job
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Job Description:
We are seeking a Digital Mixed-Signal Lead with a strong digital design and architecture background to lead the development of digital control infrastructures for advanced clocking sub-systems (PLLs, FLLs, and DLLs).
Core Responsibilities
Architecture & RTL: Own the architectural definition, RTL implementation, and system-level integration of the digital logic driving clocking IPs.
Logic Design: Design complex digital control loops, state machines for adaptive calibration, DVFS (dynamic voltage/frequency scaling) controllers, and fractional-N delta-sigma modulators.
Analog Interface: Serve as the primary bridge to Analog Circuit Designers. Translate analog specifications into robust digital architectures and define clean boundaries at the analog-digital interface.
Verification Partnership: Partner with Verification Teams to drive Mixed-Signal Verification (MSV) and Real Number Modeling (RNM) strategies for high-coverage loop simulations.
Physical Design Collaboration: Work with Physical Design Teams to co-optimize floorplanning and protect sensitive analog nodes from digital switching noise.
Sign-off Methodology: Enforce a rigorous full-chip CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) sign-off methodology for the clocking network.
Candidate Requirements
Education: Bachelors degree
Experience: 8+ years of professional digital ASIC design experience.
RTL Mastery: Deep expertise in writing robust, synthesizable SystemVerilog RTL
Process Nodes: Direct experience with advanced technology nodes, specifically N5, N3P, and beyond.
Track Record: Proven history of steering cross-functional execution from initial concept through to successful tapeouts.
Compensation and Benefits
The annual base salary range for this position is USD 121,900.00 To USD 195,000.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Source: Broadcom on Workday · View original posting (opens in new tab)
Pay in context
This role's base floor ($121,900) is above 16% of the 965 Design roles nationwide listed on this site. Their median floor is $157,419; the middle half runs from $132,000 to $184,000.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 8, 2026.
This listingMixed Signal Digital Design Lead$121,900 to $195,000
Design Verification Engineer$120K to $192K
Principal AI Development Engineer$118,800 to $190,000
PCB HW Design Engineer$121,900 to $195,000
Test Engineer (ATE)$121,900 to $195,000
Physical Design Engineer$121,900 to $195,000
Design Engineer - Flow Development$121,900 to $195,000
Chart as a table
| Role | Published base |
|---|---|
| Mixed Signal Digital Design Lead (this listing) | $121,900 - $195,000 |
| Design Verification Engineer | $120K - $192K |
| Principal AI Development Engineer | $118,800 - $190,000 |
| PCB HW Design Engineer | $121,900 - $195,000 |
| Test Engineer (ATE) | $121,900 - $195,000 |
| Physical Design Engineer | $121,900 - $195,000 |
| Design Engineer - Flow Development | $121,900 - $195,000 |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-06-30
Where this pay comes from
Location as the employer wrote it: USA-Colorado-Fort Collins-4380 Ziegler Road • USA-CA San Jose Innovation Drive
The annual base salary range for this position is USD 121,900.00 To USD 195,000.00
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
