Physical Design - CAD Lead
Company websiteefficient.computer (Efficient Computer, opens in new tab)
Base salary $180K to $260K
Employer-published annual base salary, USD. Advertised base range in PA OR Austin, TX
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationPA OR Austin, TX
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (3 h ago) · observed since
About this job
Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks—unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we're accelerating customer deployments and scaling our architecture to data center performance. Join us to build the hardware and software that bring intelligence wherever it's needed and help shape the next generation of computing.
Efficient is seeking a CAD Lead - PD flows/infrastructure to join our growing team. The ideal CAD Lead would have worked on significant portion of the full gamut of Physical Design flows and flow infrastructure (flowtracer etc). This role is in a newly formed hardware engineering group and is the seed hire for this discipline. You will get to setup CAD flows and infra from scratch and influence and shape this aspect in the future.
This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!
Key Responsibilities
- Drive and develop PD flows, methodology for state of the art finfet and multi patterning based technologies from scratch in Cadence Tempus or Synopsys Primetime.
- Help develop repeatable, predictable , design and process agnostic PD flows.
- Develop state of the art flow infrastructure to enable consistent and rapid design under tight schedule constraints for multiple product lines in the energy efficient edge AI computing market.
- Work closely with PD team leads to propose and develop end to end build and signoff flows.
- Build regression frameworks for ensuring high quality flows and achieve hardware engineering vision of spending 90% or more time on actual design tasks and NOT wrestling with tools.
- Develop collateral quality checking utils to ensure high design efficiency.
- Develop and deploy a unified environment for specifying all collaterals (stdcell, memory, PDK, hardips…) and all flow dependencies (cycle time, PVTRC corners, per flow design and process dependent configuration).
- Work with 3rd party vendor resources and coordinate their work.
- Continuously work on improving flow consistency and efficiency in the context of multiple product lines.
Required Qualifications
- Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
- Strong python other scripting programming skills.
- Experience in developing workflow orchestration infrastructure or tools for hardware development (Airflow, flowtracer etc)
- Familiarity with kubernetes and containerization
- Experience implementing regression frameworks
- SQL or other database proficiency (MongoDB ..)
- Intimate knowledge of hardware design workflows for Physical Design and RTL/DV.
- Excellent scripting skills in TCL, shell and python.
Desired Qualifications & Experience Requirements
- Experience in full chip RTL/DV and PD flows.
- Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology and its implications to physical design
- Proficiency with industry-grade physical design flow and hands-on building CAD flow infrastructure for PD engineers.
- Definition of design constraints for static timing analysis (synthesis, pre/post‑cts, sign‑off) and corners/voltage definitions.
- Experience in integrating analog or mixed-signal macro on top-level design.
- Experience in verifying IP collaterals.
We offer a competitive base salary for this role, generally ranging from $180,000 to $260,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits. Final compensation will depend on experience, level, and location, with flexibility for the right candidate.
Why Join Efficient?
Build what's next. At Efficient, you'll tackle big challenges with room to take ownership and make an impact. We back you with competitive pay, equity, a 401(k) match, company-paid benefits, paid parental leave, and flexibility—plus opportunities to grow your skills and career as we scale.
Source: Efficient Computer on Greenhouse · View original posting (opens in new tab)
Pay in context
This role's base floor ($180,000) is above 87% of the 173 Engineering (non-software) roles in Texas listed on this site; 1 other lists the same floor. Their median floor is $136,600; the middle half runs from $115,527 to $159,200.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 6, 2026.
This listingPhysical Design - CAD Lead$180K to $260K
Physical Design Engineer - Timing Lead$180K to $260K
Sr Staff Physical Design - SOC Top Lead$180K to $260K
Senior RTL Design Engineer$180K to $245K
Lead Digital Verification Engineer$200K to $260K
Computer Architect$160K to $230K
Software Build & Release Engineer$160K to $220K
Chart as a table
| Role | Published base |
|---|---|
| Physical Design - CAD Lead (this listing) | $180K - $260K |
| Physical Design Engineer - Timing Lead | $180K - $260K |
| Sr Staff Physical Design - SOC Top Lead | $180K - $260K |
| Senior RTL Design Engineer | $180K - $245K |
| Lead Digital Verification Engineer | $200K - $260K |
| Computer Architect | $160K - $230K |
| Software Build & Release Engineer | $160K - $220K |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-02-20
Where this pay comes from
Location as the employer wrote it: San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
We offer a competitive base salary for this role, generally ranging from $180,000 to $260,000, plus a 10% annual bonus, meaningful equity, and comprehens
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
