Physical Design Clocking Engineer
Company websiteintel.com (Intel, opens in new tab)
Base salary From $105,650
Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSanta Clara, CA
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (1 h ago) · observed since
About this job
Job Details:
Job Description:
As a Physical Design Engineer, you will play a critical role in the implementation of custom IP and SoC designs, transforming RTL to GDS to produce design databases ready for manufacturing. On a day-to-day basis, you will execute various aspects of the physical design flow, including synthesis, place and route, clock tree synthesis, floor planning, and static timing analysis. Your work will directly contribute to optimizing design parameters such as power, frequency, and area, impacting Intel's product innovation and delivery.
You will be part of the Data Center Group (DCG), a business unit focused on developing innovative solutions that power the future of computing. DCG works on designing advanced technologies for data centers, cloud services, and high-performance computing environments, enabling Intel's broader mission to shape the future of technology. This team provides a collaborative environment driven by technical excellence and a passion for innovation.
The primary responsibilities for this role will include, but are not limited to:
- Conduct physical design implementation tasks, including synthesis, place and route, clock tree synthesis, floor planning, and static timing analysis.
- Perform verification and signoff activities, such as equivalence verification, reliability verification, layout verification, and structural design checking.
- Analyze results and provide recommendations to resolve violations for current and future architectures.
- Optimize designs to improve product level parameters, including power, frequency, and area. -
- Participate in developing and enhancing physical design methodologies, flows, and automation processes.
- Utilize industry-standard EDA tools to execute and validate physical design processes effectively.
Qualifications:
Minimum Qualifications:
Minimum qualifications are required to be initially considered for this position.
- Bachelor's degree in a relevant field with 0-1 years of hands-on experience in physical design, demonstrating skills gained through internships, academic projects, coursework, or hands-on training OR a Master's degree in a relevant field with no prior professional experience.
- Proficiency in physical design tools, such as synthesis, place and route, and timing analysis software.
- Familiarity with EDA tools and methodologies used in physical design and verification workflows.
Preferred Qualifications:
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Strong analytical and problem-solving skills to identify and resolve design violations effectively.
- Excellent communication and collaboration abilities to contribute within a dynamic team environment.
- A proactive mindset and eagerness to learn and improve physical design methodologies and flows.
Join us in shaping the future of data-centric technology by applying your skills, curiosity, and passion for innovation.
Job Type:
College GradShift:
Shift 1 (United States of America)Primary Location:
US, California, Santa ClaraAdditional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust
N/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Source: Intel on Workday · View original posting (opens in new tab)
This listingPhysical Design Clocking EngineerFrom $105,650
CPU Physical Design EngineerFrom $105,650
SoC Debug EngineerFrom $105,650
Design Verification EngineerFrom $105,650
Ethernet System Integration EngineerFrom $105,650
GPU Logic Design EngineerFrom $105,650
Circuit Design EngineerFrom $105,650
Chart as a table
| Role | Published base |
|---|---|
| Physical Design Clocking Engineer (this listing) | From $105,650 |
| CPU Physical Design Engineer | From $105,650 |
| SoC Debug Engineer | From $105,650 |
| Design Verification Engineer | From $105,650 |
| Ethernet System Integration Engineer | From $105,650 |
| GPU Logic Design Engineer | From $105,650 |
| Circuit Design Engineer | From $105,650 |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-11-03
Where this pay comes from
Location as the employer wrote it: US, California, Santa Clara
Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USD
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
