RTL Engineer
Company websitedensityai.com (DensityAI, opens in new tab)
Base salary $215K to $300K
Employer-published annual base salary, USD. Advertised base range in Mountain View, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationMountain View, CA
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (2 h ago) · observed since
About this job
About the role
Design the RTL that defines our AI accelerator. You'll architect and implement the digital blocks — compute datapath, memory subsystem, on-chip interconnect, and control logic — from microarchitecture spec through synthesis-ready, timing-clean RTL, and own those blocks end-to-end with architecture, DV, physical design, and DFT all the way to silicon.
What You'll Do:
- Own RTL design of digital blocks/subsystems for our accelerator — microarchitecture definition, SystemVerilog implementation, and integration
- Translate architectural specs into efficient, synthesizable RTL that meets power/performance/area (PPA) targets
- Drive microarchitecture trade-offs — pipelining, datapath vs. control, clock/power gating — for high-performance, low-power design
- Partner with DV on verification, PD on synthesis/timing/floorplan closure, and DFT on testability
- Own block-level quality: synthesis, timing/constraints (SDC, STA), lint, and CDC signoff
- Contribute to architecture definition and design reviews; debug across simulation, emulation, and post-silicon bring-up
- Use and develop AI-assisted tool flows to accelerate design and verification
What We're Looking For
- Strong digital-design fundamentals and expert Verilog/SystemVerilog RTL
- 5+ years designing complex digital blocks/SoCs taken to silicon
- Solid microarchitecture skills — pipelining, datapath/control, FIFOs, arbitration, memory subsystems, on-chip interconnect/NoC
- Synthesis & timing awareness — writing synthesizable RTL, SDC constraints, STA, clock/power gating, CDC, lint
- Demonstrated collaboration with DV, PD, and DFT across the full RTL2GDS flow to tapeout
- Scripting (Python/Tcl/) for design automation
- (Optional) AI/ML accelerator or high-performance compute-datapath design; low-power techniques (UPF); high-speed interfaces (HBM, PCIe, SerDes); advanced nodes (7nm or better); RISC-V/CPU design; FPGA prototyping
Compensation
Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.
Visa Sponsorship
DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.
Export Controls
Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.
Equal Opportunity
DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.
Full compensation packages are based on candidate experience and relevant certifications.
California pay range
$215,000—$300,000 USD
Compensation
Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.
Visa Sponsorship
DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.
Export Controls
Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.
Equal Opportunity
DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.
Source: DensityAI on Greenhouse · View original posting (opens in new tab)
Pay in context
This role's base floor ($215,000) is above 91% of the 2,035 Engineering (non-software) roles in California listed on this site; 4 others list the same floor. Their median floor is $146,200; the middle half runs from $124,000 to $173,000.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 6, 2026.
This listingRTL Engineer$215K to $300K
Signal Integrity & Power Integrity Engineer$215K to $275K
PCB Quality Engineer$215K to $265K
Firmware Engineer$220K to $275K
Physical Design Timing Engineer$220K to $320K
Product Operations Engineer$200K to $285K
Physical Design Engineer$230K to $320K
Chart as a table
| Role | Published base |
|---|---|
| RTL Engineer (this listing) | $215K - $300K |
| Signal Integrity & Power Integrity Engineer | $215K - $275K |
| PCB Quality Engineer | $215K - $265K |
| Firmware Engineer | $220K - $275K |
| Physical Design Timing Engineer | $220K - $320K |
| Product Operations Engineer | $200K - $285K |
| Physical Design Engineer | $230K - $320K |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-07-01
Where this pay comes from
Location as the employer wrote it: Mountain View, CA
$215,000—$300,000 USD
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
