Six Figure Work

RTL Power Optimization Engineer – New College Grad 2026

NVIDIA

Company websitenvidia.com (NVIDIA, opens in new tab)

Base salary $116,000  to $218,500

Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA

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  • LocationSanta Clara, CA
  • WorkplaceWorkplace not stated
  • Status at last checkSource accepting applications when checked
  • Last checked (49 min ago) · observed since

About this job

Today, NVIDIA is tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. Come join the team and see how we can make a lasting impact on the world. 

Our team is privileged to work on Power Optimization of Data center, gaming and automotive GPU chips. We also work on power optimization of Networking chips. The gamut of GPUs and networking chips requires the team to provide architecture, micro-architecture, RTL Design, methodology and AI based power optimization solutions. You will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement power analysis and reduction techniques for NVIDIA's next generation GPUs and Networking products. Your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements.

What You'll Be Doing:

  • Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.

  • Use artificial intelligence to devliver RTL and/or Architecture Power optimization solutions.

  • Develop and share best practices for performing pre-silicon power analysis.

  • Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.

  • Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes.

  • Select and run a wide variety of workloads for power analysis.

  • Prototype a new architectural feature in Verilog and analyze power.

What We Need To See:

  • Pursuing or recently completed a MS or PhD in Electrical Engineering, Computer Engineering, or related fields with coursework or experience in AI, Digital Design and VLSI concepts (or equivalent experience).

  • Understanding of RTL power optimization fundamentals, including switching activity, clock/enable efficiency, and common low‑power design patterns at the RTL level.

  • Knowledge of backend flows such as logic synthesis and place‑and‑route, and how RTL decisions impact post‑layout power and timing.

  • Familiarity with RTL implementation of low‑power techniques (e.g., clock gating, operand isolation, power gating strategies, multi‑VT usage) and their trade‑offs.

  • Exposure to industry power analysis tools such as PowerArtist, PrimeTime PX, or equivalent, including running power analysis and interpreting reports to guide design changes.

  • Strong Python programming skills for building automation scripts, data pipelines, and AI/ML‑driven analysis flows for RTL power optimization.

  • Coursework and/or hands‑on experience in Machine Learning and Artificial Intelligence, with ability to apply ML techniques to EDA and silicon power problems.

  • Previous experience debugging RTL or gate‑level power anomalies by tracing logic cones, examining activity/toggle data, and identifying root‑cause structures or scenarios.

  • Strong written and verbal communication skills to document methodologies, present power findings, and explain AI/ML‑based insights to both design and tools teams.
     

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!

Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:
116,000 USD – 189,750 USD for Level 2; and 136,000 USD – 218,500 USD for Level 3.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 3, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Source: NVIDIA on Workday · View original posting (opens in new tab)

This range next to 6 other live NVIDIA roles with the nearest advertised base floor
Chart as a table
This range next to 6 other live NVIDIA roles with the nearest advertised base floor
RolePublished base
RTL Power Optimization Engineer – New College Grad 2026 (this listing)$116,000 - $218,500
Global Virtual Card Payment Administrator$116,000 - $195,500
Forward Deployed Engineer - Finance$116K - $230K
Customer Solutions Architect, Applications Engineering$116,000 - $189,750
Senior Revenue Accountant – Revenue Accounting Operations$116,000 - $195,500
ASIC Design Engineer – Clocks IP$116,000 - $218,500
Deep Learning Compiler Verification Engineer$116,000 - $189,750

Same $100K to $400K scale as every card. All NVIDIA roles · How to read the bar

Observed changes

  1. First observed on the employer's board
  2. Began meeting the published-salary criteria
Observed since
Employer-stated posting date
2026-10-30
Where this pay comes from

Location as the employer wrote it: US, CA, Santa Clara (Levels 2-3 combined)

116,000 USD – 189,750 USD for Level 2; and 136,000 USD – 218,500 USD for Level 3.

Method
Employer text, read with fixed rules and re-verified
Checked
Rule set
us-base-v2

The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.

What we verified

  • The pay figures come from the employer's own listing, quoted exactly above.
  • The pay is an annual base salary in US dollars with a minimum of at least $100,000.
  • The role was publicly listed on the employer's job board when last checked.

We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.