Six Figure Work

Senior ASIC Design Engineer - DFT

NVIDIA

Company websitenvidia.com (NVIDIA, opens in new tab)

Base salary $168,000  to $310,500

Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA

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  • LocationSanta Clara, CA
  • WorkplaceWorkplace not stated
  • Status at last checkSource accepting applications when checked
  • Last checked (33 min ago) · observed since

About this job

We are now looking for a Senior ASIC Design Engineer to join our DFT team!

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.
 

What you'll be doing:

As a key member of our DFX Methodology Team, you will play a critical role in shaping the architecture, design, implementation, and verification of DFT IPs for our next-generation SoC products. You’ll help drive innovation across the full silicon lifecycle—from pre-silicon to post-silicon—while mentoring and collaborating with cross-functional teams.

  • Own the architecture and design of fuse controller and other DFT IPs for cutting-edge SoC designs

  • Develop, deploy, and enhance DFT methodologies for scalability and future product needs

  • Define and align feature sets by working closely with architects, platform, and software teams

  • Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration

  • Create and execute test plans to support both functional and DFT full-chip verification

  • Support post-silicon bring-up and validation efforts including debug and issue resolution

  • Mentor junior engineers on test design strategies and trade-offs related to cost, quality, and performance

What we need to see:

  • BS/MS Electrical or Computer Engineering (or equivalent experience) in related domain with proven DFT experience

  • 8+ years of hands-on experience in SoC architecture, RTL design, and verification

  • Strong proficiency in micro-architecture and RTL development using Verilog. (UVM experience is a plus)

  • Experience in DFT design, methodology, and implementation

  • Familiarity with related domains such as clocking, STA, place & route, and power optimization

  • Experience in post-silicon bring-up on ATE, including understanding of pattern formats, test program development, and failure analysis

  • Proficiency in scripting languages such as Python, Perl, or Tcl

  • Excellent communication skills and a collaborative mindset—with a curiosity and passion for solving complex technical challenges

Ways to Stand out from the Crowd:

  • Experience with UVM-based verification environments

  • Experience designing fuse, eFuse, or on-chip security blocks

  • Proven track record of successfully architecting DFT IPs across multiple product generations

Why Join Us? This is an opportunity to apply your DFT and SoC architecture expertise to some of the industry’s most complex and impactful semiconductor designs. At NVIDIA, your ideas will help shape energy-efficient compute platforms used by scientists, engineers, creators, and gamers around the world. You’ll grow alongside world-class engineering teams in a collaborative, fast-paced environment that values innovation, excellence, determination, and teamwork. We offer competitive compensation, comprehensive benefits, and meaningful opportunities to advance your career.

#LI-Hybrid

Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:
168,000 USD – 264,500 USD for Level 4; and 196,000 USD – 310,500 USD for Level 5.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 3, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Source: NVIDIA on Workday · View original posting (opens in new tab)

Pay in context

This role's base floor ($168,000) is above 69% of the 3,589 Engineering (non-software) roles in California listed on this site; 85 others list the same floor. Their median floor is $147,000; the middle half runs from $125,000 to $173,075.

Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 7, 2026.

This range next to 6 other live NVIDIA roles with the nearest advertised base floor
Chart as a table
This range next to 6 other live NVIDIA roles with the nearest advertised base floor
RolePublished base
Senior ASIC Design Engineer - DFT (this listing)$168,000 - $310,500
L11 System Product Development Engineer$168,000 - $258,750
Senior Software Engineer, Network Visibility Platform - DGX Cloud$168K - $322K
Hardware Validation Procedures and Documentation Lead$168,000 - $258,750
Senior Software Engineer, Platform Engineering$168K - $322K
PhD Research Scientist, Fundamental Generative AI - New College Grad 2026$168,000 - $264,500
AI Engineering Manager - Finance$168K - $322K

Same $100K to $400K scale as every card. All NVIDIA roles · How to read the bar

Observed changes

  1. First observed on the employer's board
  2. Began meeting the published-salary criteria
Observed since
Employer-stated posting date
2026-10-30
Where this pay comes from

Location as the employer wrote it: US, CA, Santa Clara (Levels 4-5 combined)

168,000 USD – 264,500 USD for Level 4; and 196,000 USD – 310,500 USD for Level 5.

Method
Employer text, read with fixed rules and re-verified
Checked
Rule set
us-base-v2

The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.

What we verified

  • The pay figures come from the employer's own listing, quoted exactly above.
  • The pay is an annual base salary in US dollars with a minimum of at least $100,000.
  • The role was publicly listed on the employer's job board when last checked.

We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.

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