Senior FPGA Engineer, Payload Hardware Development, Leo PAA Hardware
Base salary $159,200 to $215,300
Employer-published annual base salary, USD. Advertised base range in Redmond, WA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationRedmond, WA
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (30 min ago) · observed since
About this job
LEO is Amazon’s low Earth orbit satellite broadband network. Its mission is to deliver fast, reliable internet to customers and communities around the world, and we’ve designed the system with the capacity, flexibility, and performance to serve a wide range of customers, from individual households to schools, hospitals, businesses, government agencies, and other organizations operating in locations without reliable connectivity.
The Role:
Create FPGA solutions to support LEO's satellite communication system. This is a unique opportunity to define a new system with few legacy constraints. The FPGA design engineer will work with systems teams to define/develop/implement/test/release FPGA based solutions to enable LEO. This will focus on creating digital designs for networking functions using the latest generations of FPGA technologies and modern FPGA design processes and tools.
In this role you will:
Have ownership of one or more FPGA bitstreams. - Create and release FPGAs through the development phases of uArchitecture-RTL Design-Physical Implementation-Timing Closure–Simulation Validation– Lab Based Silicon Validation
Collaborate with network communication system architects to define and design/implement/test/release/support networking functions targeted to FPGA technology
Collaborate with Digital Communications/Networking system architects and design engineers to implement digital logic functions in FPGAs.
Collaborate with system architects and design engineers to implement digital logic functions in FPGA prototypes to validate/tradeoff architecture & design alternatives
Collaborate with systems architects, HW engineering design teams & FW/SW design teams to bring up and test systems combining FPGA, firmware, RF, and Networking functions.
Drive trade-off analysis to benefit customer experience and optimization of target technology resources for cost/size/power/performance/features
Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
Key job responsibilities
-Design, develop, and implement complex FPGA architectures using Verilog HDL
-Lead FPGA design efforts for Versal ACAP and IGLOO2 platforms from concept through production
-Develop and optimize RTL code for high-performance, resource-efficient designs
-Perform timing analysis, synthesis, place and route, and design verification
-Create comprehensive test benches and simulation environments
-Collaborate with cross-functional teams including hardware engineers, software developers, and system architects
-Debug and troubleshoot FPGA designs at both simulation and hardware levels
-Develop technical documentation including design specifications, test plans, and user guides
-Support hardware integration, manufacturing, and production deployment activities
Basic Qualifications
- Bachelor's degree in Electrical Engineering or a related field with 10+ years of experience
- 7+ years of experience with Verilog and/or SystemVerilog HDL for RTL design and verification and with FPGA design tools (Vivado, Libero SoC, or equivalent)
- 7+ years of experience with simulation tools ModelSim, Vivado Simulator, or equivalent
- 5+ years of experience with UVM (SystemVerilog and/or SystemC)
- Experience with high-speed interfaces (PCIe, DDR, Ethernet, SerDes) and serial protocols (SPI, I2C, I3C, UART)
Preferred Qualifications
- Master's or Ph.D. degree in Electrical Engineering or related field with 7+ years of experience
- Experience with AMD Xilinx Versal ACAP FPGA architecture and development tools and with Microchip IGLOO2 FPGA platform
- Experience delivering products to volume production
- Experience with implementing chips with multiple power islands and power gating
- Experience with SOC bring-up and post-silicon validation
- Background in signal processing, communications, or related applications
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.
The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.
USA, WA, Redmond - 159,200.00 - 215,300.00 USD annually
Source: Amazon Leo · View original posting (opens in new tab)
This listingSenior FPGA Engineer, Payload Hardware Development, Leo PAA Hardware$159,200 to $215,300
5G NTN Payload Verification Architect, Payload Architecture Team$159,200 to $215,300
Sr HW Dev Engineer - Payload, Amazon Leo Hardware Development$159,200 to $215,300
Senior Mechanical Engineer – Spacecraft Mechanisms, Amazon Leo Mechanical - Mechanisms$159,200 to $215,300
Senior HW Dev Engineer-Payload, Leo PAA Hardware$159,200 to $215,300
Phased Array DSP & Digital Beamforming Architect, Payload Architecture Team$159,200 to $215,300
Senior HW Dev Engineer - Antenna Systems, Leo Hardware Development$159,200 to $215,300
Chart as a table
| Role | Published base |
|---|---|
| Senior FPGA Engineer, Payload Hardware Development, Leo PAA Hardware (this listing) | $159,200 - $215,300 |
| 5G NTN Payload Verification Architect, Payload Architecture Team | $159,200 - $215,300 |
| Sr HW Dev Engineer - Payload, Amazon Leo Hardware Development | $159,200 - $215,300 |
| Senior Mechanical Engineer – Spacecraft Mechanisms, Amazon Leo Mechanical - Mechanisms | $159,200 - $215,300 |
| Senior HW Dev Engineer-Payload, Leo PAA Hardware | $159,200 - $215,300 |
| Phased Array DSP & Digital Beamforming Architect, Payload Architecture Team | $159,200 - $215,300 |
| Senior HW Dev Engineer - Antenna Systems, Leo Hardware Development | $159,200 - $215,300 |
Observed changes
- Began meeting the published-salary criteria
- First observed on the employer's board
- Observed since
- Employer-stated posting date
- 2026-08-19
Where this pay comes from
Location as the employer wrote it: US, WA, Redmond
USA, WA, Redmond - 159,200.00 - 215,300.00 USD annually
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.