Senior JTAG Methodology Engineer
Company websitenvidia.com (NVIDIA, opens in new tab)
Base salary $168,000 to $310,500
Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSanta Clara, CA
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (1 h ago) · observed since
About this job
We are now looking for a Senior JTAG Methodology Engineer! As a Senior JTAG Methodology Engineer, you will architect and develop the test methodologies that make our next generation of silicon testable, debuggable, and secure from the very first bring-up. NVIDIA has crafted creative solutions for DFT architecture, verification, and post-silicon validation on some of the industry’s most complex semiconductor chips. This powerful technology changed modern computer graphics and parallel computing.
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.
What you'll be doing:
- As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, I1149.1, I1500, I1687, 1838, memory BIST, memory dump and DFX security methodology.
- You will partner closely with timing, physical design, software, bring-up, and production teams to make the right trade-offs between cost and quality.
- In addition, you will help architect, develop and deploy DFT methodologies for our next generation products including RTL design, Verification, pattern generation, partnering with teams like timing, physical design, software, bringup, production
- You will also help mentor junior engineers on test designs and trade-offs including cost and quality.
What we need to see:
- BS/MS Electrical or Computer Engineering (or equivalent experience) in related domain with proven DFT experience
- 10+ years of hands-on experience in SoC architecture, RTL design, and verification.
- Strong analytical skills, with experience using vendor tools to verify and validate test patterns and logic on highly complex, multi-million-gate designs.
- Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
- Experience in JTAG, Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development
- Exceptional written and oral interpersonal skills with the curiosity to work on rare challenges
Ways to Stand out from the Crowd:
- Knowledge of DFT security and hardware system security is a plus.
- Strong programming and scripting skills in Perl, Python, or Tcl
- Proven track record of successfully deploying advanced DFT methodologies in groundbreaking semiconductor technologies
- Experience mentoring engineers and driving methodology adoption across multiple product generations
- Strong problem-solving skills and a proactive approach to overcoming technical challenges
Why Join Us? This is an opportunity to apply your DFT and SoC architecture expertise to some of the industry’s most complex and impactful semiconductor designs. At NVIDIA, your ideas will help shape energy-efficient compute platforms used by scientists, engineers, creators, and gamers around the world. You’ll grow alongside world-class engineering teams in a collaborative, fast-paced environment that values innovation, excellence, determination, and teamwork. We offer competitive compensation, comprehensive benefits, and meaningful opportunities to advance your career.
#LI-Hybrid
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:168,000 USD – 264,500 USD for Level 4; and 196,000 USD – 310,500 USD for Level 5.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.Source: NVIDIA on Workday · View original posting (opens in new tab)
This listingSenior JTAG Methodology Engineer$168,000 to $310,500
L11 System Product Development Engineer$168,000 to $258,750
Senior Software Engineer, Network Visibility Platform - DGX Cloud$168K to $322K
Hardware Validation Procedures and Documentation Lead$168,000 to $258,750
Senior Software Engineer, Platform Engineering$168K to $322K
PhD Research Scientist, Fundamental Generative AI - New College Grad 2026$168,000 to $264,500
AI Engineering Manager - Finance$168K to $322K
Chart as a table
| Role | Published base |
|---|---|
| Senior JTAG Methodology Engineer (this listing) | $168,000 - $310,500 |
| L11 System Product Development Engineer | $168,000 - $258,750 |
| Senior Software Engineer, Network Visibility Platform - DGX Cloud | $168K - $322K |
| Hardware Validation Procedures and Documentation Lead | $168,000 - $258,750 |
| Senior Software Engineer, Platform Engineering | $168K - $322K |
| PhD Research Scientist, Fundamental Generative AI - New College Grad 2026 | $168,000 - $264,500 |
| AI Engineering Manager - Finance | $168K - $322K |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-10-30
Where this pay comes from
Location as the employer wrote it: US, CA, Santa Clara (Levels 4-5 combined)
168,000 USD – 264,500 USD for Level 4; and 196,000 USD – 310,500 USD for Level 5.
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
