Senior Silicon Engineer
Company websitegetclera.com (Clera, opens in new tab)
Base salary $200K to $300K
Employer-published annual base salary, USD. Advertised base range in San Francisco, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSan Francisco, CA
- WorkplaceOn-site
- Status at last checkSource accepting applications when checked
- Last checked (2 h ago) · observed since
About this job
About the Role
Lead silicon design for an AI accelerator, taking designs from FPGA prototypes through ASIC tapeout and bring-up. As a senior member of a small hardware team, you will shape technical direction across architecture, RTL, verification, and tooling, working closely with PCB, interconnect, software, and systems teams.
What You'll Do
Lead FPGA prototype development and optimization, from design specifications through deployment on working hardware.
Design and review synthesizable RTL for an ASIC, with a focus on clean microarchitecture.
Build and improve lint, simulation, synthesis, timing, and verification flows for rapid iteration and tapeout readiness.
Make architecture decisions across compute datapaths, memory systems, on-chip interconnect, and control logic.
Drive design through tapeout, bring-up, and delivery milestones, contributing hands-on during critical periods.
Mentor teammates and help grow the silicon engineering team.
What We're Looking For
At least 8 years of experience in digital design or silicon engineering, building RTL, FPGA prototypes, or ASICs.
Experience shipping synthesizable SystemVerilog or Verilog in production silicon or FPGA designs, and taking FPGA designs from RTL through synthesis, place-and-route, and deployment to working hardware.
Strong understanding of digital design, including pipelining, clocks, resets, latency, throughput, and microarchitecture.
Experience designing compute datapaths and memory systems with bandwidth and latency constraints.
Hands-on experience with simulation, linting, synthesis, SDC constraints, timing closure, and CDC verification.
Experience automating hardware flows with Python, Tcl, Make, Nix, or similar tools, plus background in AI accelerators or low-level AI kernels.
Tapeout experience, high-speed interfaces, formal verification, UVM, cocotb, firmware, or systems-level hardware drivers are valuable.
Compensation & Benefits
Base salary is $200,000 to $300,000 USD annually. Visa sponsorship is available.
Location
Full-time, on-site role in San Francisco, United States. This position is not remote or hybrid.
Source: Clera on Ashby · View original posting (opens in new tab)
This listingSenior Silicon Engineer$200K to $300K
Founding Product Engineer$200K to $250K
Founding Engineer$200K to $300K
Founding Enterprise Account Executive$200K to $250K
Founding Engineering Lead$200K to $400K
Founding DevOps Engineer$200K to $300K
Founding Product Engineer$200K to $250K
Chart as a table
| Role | Published base |
|---|---|
| Senior Silicon Engineer (this listing) | $200K - $300K |
| Founding Product Engineer | $200K - $250K |
| Founding Engineer | $200K - $300K |
| Founding Enterprise Account Executive | $200K - $250K |
| Founding Engineering Lead | $200K - $400K |
| Founding DevOps Engineer | $200K - $300K |
| Founding Product Engineer | $200K - $250K |
Observed changes
- Began meeting the published-salary criteria
- First observed on the employer's board
- Observed since
- Employer-stated posting date
- 2026-10-15
Where this pay comes from
Location as the employer wrote it: San Francisco
Base salary is $200,000 to $300,000 USD annually. Visa sponsorship is available.
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
