Senior STA Signoff Methodology Engineer
Company websitenvidia.com (NVIDIA, opens in new tab)
Base salary $168,000 to $310,500
Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA +1 more
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSanta Clara, CA +1 more
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (21 min ago) · observed since
All places named
- Santa Clara, CA
- Austin, TX
About this job
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
We are seeking an innovative Senior STA Signoff Methodology Engineer to help drive sign-off strategies for the world's leading GPUs, CPUs, LPUs and SoCs. This position is a broad opportunity to optimize performance, yield, and reliability through increasingly comprehensive modeling, insightful analysis, and automation. This work will influence the entire next generation AI landscape through critical contributions across NVIDIA's many product lines. We have crafted a team of highly motivated people whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. If you are fascinated by the immense scale of precision, craftsmanship, and artistry required to make billions of transistors function on every die at technology nodes as deep as 3nm and beyond, this is an ideal role.
What you'll be doing:
Run large-scale SPICE simulations and STA experiments to model the impact of advanced technologies on chip timing.
Develop STA and PNR flows and recommendations addressing aging, self-heating, thermal effects, IR drop, electro migration, and other advanced-node physical effects.
Collaborate with technology leads, physical-design engineers, and timing engineers to define and deploy sophisticated timing-signoff strategies for extraordinary silicon performance.
Develop tools and methodologies that improve design performance, predictability, and silicon reliability beyond the capabilities of standard EDA tools.
Work across STA, constraints, and timing and power optimization.
Perform extensive data analysis using Python, JMP, or similar tools to improve STA-to-silicon correlation.
What we need to see:
MS in Electrical or Computer Engineering, or equivalent experience, with 8 years of experience in ASIC design and timing.
Solid understanding of RC extraction, device physics, STA methodologies, and EDA-tool limitations.
Proven foundation in the mathematics and physics underlying electrical design.
Experience with low-power techniques, including multi-Vt design, clock gating, power gating, activity-based power analysis, DVFS, and CDC.
Understanding of signal and power integrity, crosstalk, electromigration, noise, OCV, timing margins, clock jitter, and IR drop.
Understanding of standard-cell, memory, and I/O IP modeling and their use in ASIC flows.
Hands-on experience with advanced FinFET and emerging CMOS technologies at 5 nm, 3 nm, 2 nm, and beyond.
Familiarity with industry-standard ASIC tools such as PrimeTime, ICC2, RedHawk, and Tempus.
Strong communication skills and a collaborative working style.
Ways to stand out from the crowd:
Familiarity with 3D IC integration, die stacking and packaging, self-heating, and their impact on timing closure.
Strong data-analysis and modeling skills employing Python, JMP, or similar platforms.
Proficiency in Tcl and Python; C++ experience is a plus.
NVIDIA is widely considered one of the technology world's most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're an engineer who thinks in systems, takes pride in designing things that last, and wants to see the silicon your work helps produce — we want to hear from you.
Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:168,000 USD – 264,500 USD for Level 4; and 196,000 USD – 310,500 USD for Level 5.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.Source: NVIDIA on Workday · View original posting (opens in new tab)
Pay in context
This role's base floor ($168,000) is above 70% of the 3,580 Engineering (non-software) roles in California listed on this site; 85 others list the same floor. Their median floor is $147,000; the middle half runs from $125,000 to $173,000.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 8, 2026.
This listingSenior STA Signoff Methodology Engineer$168,000 to $310,500
L11 System Product Development Engineer$168,000 to $258,750
Senior Software Engineer, Network Visibility Platform - DGX Cloud$168K to $322K
Hardware Validation Procedures and Documentation Lead$168,000 to $258,750
Senior Software Engineer, Platform Engineering$168K to $322K
PhD Research Scientist, Fundamental Generative AI - New College Grad 2026$168,000 to $264,500
AI Engineering Manager - Finance$168K to $322K
Chart as a table
| Role | Published base |
|---|---|
| Senior STA Signoff Methodology Engineer (this listing) | $168,000 - $310,500 |
| L11 System Product Development Engineer | $168,000 - $258,750 |
| Senior Software Engineer, Network Visibility Platform - DGX Cloud | $168K - $322K |
| Hardware Validation Procedures and Documentation Lead | $168,000 - $258,750 |
| Senior Software Engineer, Platform Engineering | $168K - $322K |
| PhD Research Scientist, Fundamental Generative AI - New College Grad 2026 | $168,000 - $264,500 |
| AI Engineering Manager - Finance | $168K - $322K |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-10-30
Where this pay comes from
Location as the employer wrote it: US, CA, Santa Clara • US, TX, Austin (Levels 4-5 combined)
168,000 USD – 264,500 USD for Level 4; and 196,000 USD – 310,500 USD for Level 5.
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
