Signal Integrity and PCB Design Engineer
Company websitenvidia.com (NVIDIA, opens in new tab)
Base salary $116,000 to $218,500
Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSanta Clara, CA
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (22 min ago) · observed since
About this job
We are looking for a Signal Integrity & PCB design Engineer! NVIDIA is powering the next wave of AI and accelerated computing, and our PCB technology is a critical enabler of the world's highest-performance systems. Join our SI team to ensure that every board we ship meets the most demanding signal integrity requirements — from early material research through high-volume manufacturing. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.
If you love solving complex signal integrity challenges and thrive on bridging the gap between design intent and manufacturing reality, we want to hear from you.
What you'll be doing:
- Lead SI design activities, PCB stackup design, material selection, design guide implementation and post-layout analysis
- System-level signal integrity simulation of PCIE, LPDDR/DDR/GDDR, MIPI, HDMI, USB and other interfaces.
- Analyze and optimize Power delivery network (PDN) on PCBs.
- Work closely with Package and PCB Design teams crafting solutions for system SI/PI performance
- TDR & VNA measurement for PKG/PCB material characterization and model correlation
What we need to see:
- BS/MS in Electrical Engineering (or equivalent experience) with minimum 2+ years of experience as a SI/PI engineer
- Deep understanding of electromagnetics, transmission line theory and various channel components.
- Experienced with Cadence Allegro PCB designer and Constraints Manager and or other PCB stackup designer tools
- Understanding of impacts of high-volume PCB manufacturing on channel signal integrity
- Experience with SI channel design solutions for industry standard interface like PCIE, DRAM, MIPI, HDMI, USB etc.
- Hands on experience with HFSS, Sigrity, Hspice and/or similar industry standard tools
Ways to stand out from the crowd:
- Experience of SI/PI design sign off process at platform level
- Familiarity with PCB fabrication process, understanding of PCB and package material choice impact on SI performance
- Familiarity with high-speed transmitter, receiver design, and various equalization schemes
116,000 USD – 189,750 USD for Level 2; and 136,000 USD – 218,500 USD for Level 3.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.Source: NVIDIA on Workday · View original posting (opens in new tab)
Pay in context
This role's base floor ($116,000) is above 15% of the 3,581 Engineering (non-software) roles in California listed on this site; 24 others list the same floor. Their median floor is $147,000; the middle half runs from $125,000 to $173,000.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 8, 2026.
This listingSignal Integrity and PCB Design Engineer$116,000 to $218,500
Global Virtual Card Payment Administrator$116,000 to $195,500
Forward Deployed Engineer - Finance$116K to $230K
Customer Solutions Architect, Applications Engineering$116,000 to $189,750
Senior Revenue Accountant – Revenue Accounting Operations$116,000 to $195,500
ASIC Design Engineer – Clocks IP$116,000 to $218,500
Deep Learning Compiler Verification Engineer$116,000 to $189,750
Chart as a table
| Role | Published base |
|---|---|
| Signal Integrity and PCB Design Engineer (this listing) | $116,000 - $218,500 |
| Global Virtual Card Payment Administrator | $116,000 - $195,500 |
| Forward Deployed Engineer - Finance | $116K - $230K |
| Customer Solutions Architect, Applications Engineering | $116,000 - $189,750 |
| Senior Revenue Accountant – Revenue Accounting Operations | $116,000 - $195,500 |
| ASIC Design Engineer – Clocks IP | $116,000 - $218,500 |
| Deep Learning Compiler Verification Engineer | $116,000 - $189,750 |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-10-30
Where this pay comes from
Location as the employer wrote it: US, CA, Santa Clara (Levels 2-3 combined)
116,000 USD – 189,750 USD for Level 2; and 136,000 USD – 218,500 USD for Level 3.
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.