Sr Principal Engineer AI/ML
Company websitegf.com (GlobalFoundries, opens in new tab)
Base salary $171K to $325K
Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA +2 more
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSanta Clara, CA +2 more
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (21 min ago) · observed since
All places named
- Santa Clara, CA
- Austin, TX
- Richardson
About this job
About GlobalFoundries
GlobalFoundries (GF) is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GF makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.
Summary of Role:
We are seeking an experienced CPU IP Design Engineer. Responsible for Defining, leading and owning RTL development of our latest AI-enabled RISC-V CPU core. The candidate will be responsible for all aspects of the design including Functional Features, Performance, Power, and Area.
Essential Responsibilities:
Drive the micro-architecture and design of critical blocks of the CPU core
Design of RISC-V Vector CPU core and its custom extensions
Design of AI-enabled Matrix engine to augment the Vector CPU
Explore high-performance strategies working with the CPU modeling team
Perform Microarchitecture development and specification- from early high-level architectural exploration, through microarchitectural research and arrive at detailed specifications
Configure Design Features Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals
Perform Functional verification support and assist in the design verification strategy
Assist with the verification of RTL design performance goals
Partner with a multi-functional engineering team to implement and validate physical design aspects of timing, area, reliability, testability, and power
Other Responsibilities:
Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.
Required Qualifications:
Hands-on working knowledge of the pipeline stages of an in-order or out-of-order high-performance CPU core
Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas:
* Instruction fetch and decode, branch prediction techniques
* Instruction scheduling, register renaming, Reorder Buffer (ROB)
* Out-of-order execution
* Integer and Floating-point execution
* Load/Store execution
* Instruction and Data Prefetch
* Vector data path
* Cache and memory subsystems
Knowledge of Cache coherency and memory consistency
Knowledge of System Verilog, Verilog and/or VHDL
Experience with simulators and waveform debugging tools.
Knowledge of logic design principles along with timing and power implications
Master’s with 10+ years of experience, PhD 5+ years of work experience
Preferred Qualifications:
Experience with designing RISC-V, ARM, and/or MIPS CPU
Experience with Hardware multi-threading, virtualization, and SIMD designs
Experience with vector and matrix-enabled CPUs, preferably RISC-V processors.
Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
Understanding of low-power microarchitecture techniques
Experience using a scripting language such as Perl or Python
Understanding of CPU integration at SoC level
Understanding of Safety and Security microarchitecture
Expected Salary Range
$171,000.00 - $325,000.00The exact Salary will be determined based on qualifications, experience and location.
If you need a reasonable accommodation for any part of the employment process, please contact us by email at [email protected] and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.
An offer with GlobalFoundries is conditioned upon the successful completion of pre-employment conditions, as applicable, and subject to applicable laws and regulations.
GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential. GlobalFoundries goal of excellence in business necessitates the attraction and retention of highly qualified people. Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory.
All policies and processes which pertain to employees including recruitment, selection, training, utilization, promotion, compensation, benefits, extracurricular programs, and termination are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law
Source: GlobalFoundries on Workday · View original posting (opens in new tab)
This listingSr Principal Engineer AI/ML$171K to $325K
Deputy Director, Product Platforms$171K to $296K
Sr Principal Engineer - Test Development and Automation$171K to $296K
Bench Validation and Characterization Manager$171K to $296K
System Architect, Custom Silicon$171K to $296K
SAP FICO Solution Architect$167,149 to $208,000
Sr Mgr/Dep Director ASIC Digital Design IP ENGINEERING$167K to $275K
Chart as a table
| Role | Published base |
|---|---|
| Sr Principal Engineer AI/ML (this listing) | $171K - $325K |
| Deputy Director, Product Platforms | $171K - $296K |
| Sr Principal Engineer - Test Development and Automation | $171K - $296K |
| Bench Validation and Characterization Manager | $171K - $296K |
| System Architect, Custom Silicon | $171K - $296K |
| SAP FICO Solution Architect | $167,149 - $208,000 |
| Sr Mgr/Dep Director ASIC Digital Design IP ENGINEERING | $167K - $275K |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-09-18
Where this pay comes from
Location as the employer wrote it: Santa Clara • Richardson • Austin
$171,000.00 - $325,000.00
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
