Six Figure Work

Cell Modeling and Verification Engineer - New College Grad 2026

NVIDIA

Company websitenvidia.com (NVIDIA, opens in new tab)

Base salary $100,000  to $189,750

Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA

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  • LocationSanta Clara, CA
  • WorkplaceWorkplace not stated
  • Status at last checkSource accepting applications when checked
  • Last checked (27 min ago) · observed since

About this job

Our work at NVIDIA is dedicated towards a computing model focused on visual and AI computing. For two decades, NVIDIA has pioneered visual computing, the art and science of computer graphics, with our invention of the GPU. The GPU has also shown to be spectacularly effective at solving some of the most complex problems in computer science. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots and self-driving cars that can perceive and understand the world. We are looking to grow our company and teams with the smartest people in the world and there has never been a more exciting time to join our team!

The NVIDIA VLSI team is looking for a Cell Modeling and Verification Engineer with strong experience in hardware design and methodologies to help develop NVIDIA's ground breaking ASIC products and work hands on with new NVIDIA hardware to ensure it meets design, feature, and quality objectives. Our team is at the intersection of circuit design and digital design to help craft the most power-efficient and performance leading SoCs and GPUs to push the state of the art ASIC Verilog modelling.

What you will be doing:

  • Work with sophisticated technologies and develop behavioral model and verification for custom mixed signal design cells that would be used on all the NVIDIA products.
  • Use Verilog, SystemVerilog, Perl, or Python and understanding of PLL and other high-speed interconnects to model, verify, emulate/prototype mixed-signal designs.
  • Collaborate with cross function teams with regards to library build, cell integration, ASIC verification and DFT simulation.
  • Document, implement, and deliver fully verified and high performance RTL to achieve design targets.

What we need to see:

  • Bachelors or Masters in Electrical Engineering or Computer Engineering (or equivalent experience).
  • Hands-on experience with RTL simulation and waveform debug.
  • Strong understanding of Verilog HDL.
  • Scripting experiences and skills using Python or Perl.
  • Knowledge of fundamental digital design and logic design concepts.

Ways to stand out from the crowd:

  • Previous digital design experience is a plus.
  • Previous experience running simulations in Verilog.
  • Shown ability to collaborate with many groups and communicate technical details.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!

Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:
100,000 USD – 166,750 USD for Level 1; and 116,000 USD – 189,750 USD for Level 2.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 3, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Source: NVIDIA on Workday · View original posting (opens in new tab)

Pay in context

This role's base floor ($100,000) is above 0% of the 3,589 Engineering (non-software) roles in California listed on this site; 203 others list the same floor. Their median floor is $147,000; the middle half runs from $125,000 to $173,075.

Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 7, 2026.

This range next to 6 other live NVIDIA roles with the nearest advertised base floor
Chart as a table
This range next to 6 other live NVIDIA roles with the nearest advertised base floor
RolePublished base
Cell Modeling and Verification Engineer - New College Grad 2026 (this listing)$100,000 - $189,750
ASIC Verification Engineer, Memory Management - New College Grad 2027$100,000 - $189,750
Low Power ASIC Engineer - New College Grad 2027$100,000 - $189,750
ASIC Verification Engineer - New College Grad 2027$100,000 - $189,750
High Speed SerDes Validation Engineer - New College Grad 2026$100,000 - $189,750
Formal Verification Engineer - New College Grad 2027$100,000 - $189,750
GPU Verification Engineer - New College Grad 2026$100,000 - $189,750

Same $100K to $400K scale as every card. All NVIDIA roles · How to read the bar

Observed changes

  1. First observed on the employer's board
  2. Began meeting the published-salary criteria
Observed since
Employer-stated posting date
2026-10-30
Where this pay comes from

Location as the employer wrote it: US, CA, Santa Clara (Levels 1-2 combined)

100,000 USD – 166,750 USD for Level 1; and 116,000 USD – 189,750 USD for Level 2.

Method
Employer text, read with fixed rules and re-verified
Checked
Rule set
us-base-v2

The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.

What we verified

  • The pay figures come from the employer's own listing, quoted exactly above.
  • The pay is an annual base salary in US dollars with a minimum of at least $100,000.
  • The role was publicly listed on the employer's job board when last checked.

We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.

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