Design Automation Engineer (TFM/EDA)
Company websiteintel.com (Intel, opens in new tab)
Base salary From $137,610
Employer-published annual base salary, USD. Advertised base range in Folsom, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationFolsom, CA
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (1 h ago) · observed since
All 4 locations
- US, California, Folsom
- US, Oregon, Hillsboro
- US, California, Santa Clara
- US, Arizona, Phoenix
About this job
Job Details:
Job Description:
The Role and Impact
As an Infrastructure and DevOps Engineer at Intel Foundry, you will play a vital role in enabling and optimizing design environments that support advanced semiconductor development. You will focus on installing, maintaining, and providing technical support for design automation scripts, front-end and back-end tools, workflows, and licenses. Your contributions will help ensure seamless integration of new tools and methods, driving design processes efficiently and effectively.
Business Group
Intel Foundry is a cornerstone of Intel's mission to revolutionize semiconductor manufacturing and design. The Infrastructure and Solutions team within Intel Foundry focuses on delivering robust, scalable, and innovative solutions that empower Intel's engineering teams to achieve breakthrough results. By joining this group, you'll be contributing to Intel Foundry's goal of advancing technological innovation and supporting the design of next-generation products.
Key Responsibilities
- Resolve tool/methodology issues encountered during the design path to TapeOut.
- Provide training and documentation support for design ramp-up activities.
- Collaborate with EDA providers to ensure required tool features meet project quality expectations.
- Partner closely with PDK/library experts, flow development teams, and product design teams to drive workflow improvements.
- Work with engineering compute teams to provision adequate compute capacity and troubleshoot associated issues.
- Develop automation for the installation and optimization of design environments, including PDKs, EDA tools, and licenses.
- Support the seamless integration of new tools and methods into existing workflows, ensuring scalability and adoption across design teams.
Qualifications:
Minimum Qualifications
- US Citizenship required.
- Ability to obtain a US Government Security Clearance TS/SCI.
- Bachelor's degree in relevant field with 6+ years of hands-on experience in infrastructure and DevOps roles OR a Master's degree with 4+ years of experience OR a PhD with 2+ years of experience.
- Experience with front-end and back-end EDA tools, flows, and methodologies, including debugging and problem-solving.
Knowledge of physical design optimization and tools flows/methodologies (TFM). - Experience with scripting languages such as Tcl, Perl, Python, and familiarity with Verilog/VHDL.
- Expertise in Linux-based environments, including bash and tcsh.
Preferred Qualifications
- Hands-on experience with industry-standard front-end and back-end EDA tool installations.
- Experience with installing foundry PDKs and flows, including tools like Cheetah.
- Experience with debugging and design automation.
Join our team and contribute to shaping the future of semiconductor innovation while growing your expertise in a dynamic, collaborative environment.
Job Type:
Experienced HireShift:
Shift 1 (United States of America)Primary Location:
US, California, FolsomAdditional Locations:
US, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, HillsboroPosting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust
N/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $137,610.00-265,870.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Source: Intel on Workday · View original posting (opens in new tab)
Pay in context
This role's base floor ($137,610) is above 16% of the 4,664 Software Engineering roles in California listed on this site; 2 others list the same floor. Their median floor is $176,500; the middle half runs from $149,100 to $204,000.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 7, 2026.
This listingDesign Automation Engineer (TFM/EDA)From $137,610
Factory Construction Project / Program ManagerFrom $140,220
Senior Capacity and Strategic Planning EngineerFrom $140,830
Sr Back-End Facilities Development EngineerFrom $140,830
Packaging Quality and Reliability EngineerFrom $140,830
Senior Facilities Mechanical EngineerFrom $140,830
Senior Product Failure Analysis EngineerFrom $140,830
Chart as a table
| Role | Published base |
|---|---|
| Design Automation Engineer (TFM/EDA) (this listing) | From $137,610 |
| Factory Construction Project / Program Manager | From $140,220 |
| Senior Capacity and Strategic Planning Engineer | From $140,830 |
| Sr Back-End Facilities Development Engineer | From $140,830 |
| Packaging Quality and Reliability Engineer | From $140,830 |
| Senior Facilities Mechanical Engineer | From $140,830 |
| Senior Product Failure Analysis Engineer | From $140,830 |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-10-28
Where this pay comes from
Location as the employer wrote it: Multiple locations (4)
Annual Salary Range for jobs which could be performed in the US: $137,610.00-265,870.00 USD
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.