Design Verification Engineer
Company websitebroadcom.com (Broadcom, opens in new tab)
Base salary $143,800 to $230,000
Employer-published annual base salary, USD. Advertised base range in Broomfield, CO +4 more
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationBroomfield, CO +4 more
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (1 h ago) · observed since
All 5 locations
- USA-CO Broomfield
- USA-CA-San Diego-West Bernardo
- USA-Colorado-Fort Collins-4380 Ziegler Road
- USA-CA San Jose Innovation Drive
- USA-CA Irvine Alton Parkway Bldg 1
About this job
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Job Description:
Design Verification Engineer
Broadcom's ASIC Products Division (APD), a worldwide leader in the design of complex custom ASICs and embedded IP, is looking for an experienced verification engineer that will be responsible for modeling and verification activities related to complex digital and mixed signal (MXS) IP blocks used in Broadcom’s ASIC developments.
The engineer will be responsible for defining verification plans and environment architecture, developing test cases and test bench components, coverage analysis and closure, and debug. This position may involve working with emulation and FPGA prototyping platforms and leading efforts in evaluating and driving the adoption of advanced verification methodologies/flows. The engineer will be expected to develop functional models to facilitate the block, system, and ASIC level verification. The candidate must work closely with the design teams and EDA vendors to accomplish the modeling and verification tasks.
The candidate must have experience using SystemVerilog and UVM, designing verification components including UVM agents, checkers, and behavioral models. Experience with implementing and achieving coverage goals by developing random & directed test cases, and SystemVerilog Assertions. This engineer will be responsible for analyzing and debugging simulation failures at the RTL and gate-level. The engineer must be knowledgeable of RTL, gate-level netlists, and SDF and capable of analyzing such formats in the verification context.
Requirements:
12+ years of experience with verification concepts and architectures for complex digital and MXS circuits
Experience verifying designs at the block and system levels.
Experience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC)
Experience debugging RTL and gate-level netlists, analyzing schematic diagrams of analog / MXS circuits
Experience using SystemVerilog and advanced verification concepts and methodologies (UVM, SVA)
Experience with Synopsys, Cadence, and Mentor simulations tools
Demonstrated ability to plan and deploy complex, reusable, and scalable verification environments
Experience with Perl/Python and Tcl or other scripting languages
Experience with version control systems (DesignSync, git)
Superior writing, grammar, and verbal communication skills
Excellent problem solver; develops and employs automated processes where applicable
Worked independently and in a global team and dynamic environment in a highly visible role
Possesses ability to learn and adapt to new tools and methodologies on the fly
Must have legal authorization to work in the US
It is a plus if the candidate has expertise in one or more of the following areas:
Experience with hardware design and debug
Experience with emulation (Palladium, Veloce, Zebu) and FPGA (Xilinx) platforms
Formal verification concepts / experience is a plus
Experience with verifying iJTAG network using ICL and PDL in the Tessent tool a plus
Experience with co-simulation a plus
Education and Experience required:
BS in Electrical Engineering / Computer Engineering and 12+ years of related experience; or an MS in Electrical Engineering / Computer Engineering and 10+ years of related experience.
Compensation and Benefits
The annual base salary range for this position is USD 143,800.00 To USD 230,000.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Source: Broadcom on Workday · View original posting (opens in new tab)
Pay in context
This role's base floor ($143,800) is above 58% of the 4,274 Engineering (non-software) roles nationwide listed on this site; 13 others list the same floor. Their median floor is $136,500; the middle half runs from $116,800 to $160,000.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 7, 2026.
This listingDesign Verification Engineer$143,800 to $230,000
R&D Engineer IC Design 5$143,800 to $230,000
DFT Lead Engineer$143,800 to $230,000
Principal Physical Design Engineer$143,800 to $230,000
Staff Software Engineer$143,800 to $230,000
R&D Engineer Software 5$143,800 to $230,000
Physical Design Engineer$143,800 to $230,000
Chart as a table
| Role | Published base |
|---|---|
| Design Verification Engineer (this listing) | $143,800 - $230,000 |
| R&D Engineer IC Design 5 | $143,800 - $230,000 |
| DFT Lead Engineer | $143,800 - $230,000 |
| Principal Physical Design Engineer | $143,800 - $230,000 |
| Staff Software Engineer | $143,800 - $230,000 |
| R&D Engineer Software 5 | $143,800 - $230,000 |
| Physical Design Engineer | $143,800 - $230,000 |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-08-04
Where this pay comes from
Location as the employer wrote it: Multiple locations (5)
The annual base salary range for this position is USD 143,800.00 To USD 230,000.00
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
