Lead Hardware Design Validation Engineer - Memory Subsystem
Company websitenvidia.com (NVIDIA, opens in new tab)
Base salary $168K to $322K
Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSanta Clara, CA
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (1 h ago) · observed since
About this job
Widely considered to be one of the technology world’s most desirable employers, NVIDIA is an industry leader with groundbreaking developments in High-Performance Computing, Artificial Intelligence and Visualization. The GPU, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. Our work opens up new universes to explore, enables amazing creativity and discovery and powers what were once science fiction inventions from artificial intelligence to autonomous cars. NVIDIA is leading the way in groundbreaking developments in Artificial Intelligence, High-Performance Computing and Visualization. NVIDIA’s System Product Team is looking for curious, collaborative, and motivated hardware engineers to take our GPU memory subsystem from first silicon power-on to production.
What you will be doing:
Hands-on leadership of HBM/GDDR enablement, validation, and failure analysis for NVIDIA’s datacenter and graphics products.
Drive review of memory partner’s design limits and test methodology. Integrate learnings into unique characterization and test plans for each memory generation.
Apply understanding of controller design, board design, and DRAM design to define and refine characterization, validation, and POR set methodologies.
Work closely with memory partners to successfully enable memory into production.
Work cross-functionally with multiple hardware design and software teams.
Guide product level decisions for the memory subsystem that span ASIC/VLSI/Board/ATE.
What we need to see:
Masters or higher in Electrical engineering (or equivalent experience).
10+ years of relevant hands-on experience in high-speed DRAM design and test.
Broad comprehension of ASIC design, mixed signal design, and power/signal integrity concepts.
Strong fundamentals in science, engineering, and data analysis.
Very comfortable being hands-on with hardware and software.
Working knowledge of Linux, scripting, programming, computer systems, and data analysis methods.
168,000 USD – 258,750 USD for Level 4; and 200,000 USD – 322,000 USD for Level 5.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.Source: NVIDIA on Workday · View original posting (opens in new tab)
This listingLead Hardware Design Validation Engineer - Memory Subsystem$168K to $322K
L11 System Product Development Engineer$168,000 to $258,750
Senior Software Engineer, Network Visibility Platform - DGX Cloud$168K to $322K
Hardware Validation Procedures and Documentation Lead$168,000 to $258,750
Senior Software Engineer, Platform Engineering$168K to $322K
AI Engineering Manager - Finance$168K to $322K
Senior Technical Program Manager – DFX Software Methodology$168K to $322K
Chart as a table
| Role | Published base |
|---|---|
| Lead Hardware Design Validation Engineer - Memory Subsystem (this listing) | $168K - $322K |
| L11 System Product Development Engineer | $168,000 - $258,750 |
| Senior Software Engineer, Network Visibility Platform - DGX Cloud | $168K - $322K |
| Hardware Validation Procedures and Documentation Lead | $168,000 - $258,750 |
| Senior Software Engineer, Platform Engineering | $168K - $322K |
| AI Engineering Manager - Finance | $168K - $322K |
| Senior Technical Program Manager – DFX Software Methodology | $168K - $322K |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-10-30
Where this pay comes from
Location as the employer wrote it: US, CA, Santa Clara (Levels 4-5 combined)
168,000 USD – 258,750 USD for Level 4; and 200,000 USD – 322,000 USD for Level 5.
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
