Senior ASIC Design Engineer - Memory Subsystem
Company websitenvidia.com (NVIDIA, opens in new tab)
Base salary $136,000 to $264,500
Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSanta Clara, CA
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (1 h ago) · observed since
About this job
Today, NVIDIA is tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. Come join the team and see how we can make a lasting impact on the world.
NVIDIA is looking for an Senior ASIC Design Engineer to join our Memory Subsystem Team!
What you'll be doing:
- As a member of our Memory Subsystem Design team, you will collaborate with architects/design verification/formal verification/physical design team to deliver a world-class solution. NVIDIA SOC Interconnects, ordering controllers and memory accelerators are among the industry's most sophisticated because of the complex area, latency, power, bandwidth and quality-of-service requirements.
- In this position, you will have the opportunity to be responsible for the micro-architecture and design including RTL design, synthesis and timing analysis using innovative CAD tools and using the latest process technologies.
What we need to see:
- BS or MS in Electrical Engineering or Computer Engineer or related degree (or equivalent experience)
- 5+ years of experience
- Experience with high-speed coherent interconnects, protocol bridges, hardware-managed coherency and system level caches is a plus
- Experience with multiple clock domains and asynchronous interfaces is a plus
- Knowledge of industry specifications like CHI/CXL/PCI-E is a plus.
- Strong proficiency of Verilog or VHDL.
- Scripting language like PERL
NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.Source: NVIDIA on Workday · View original posting (opens in new tab)
Pay in context
This role's base floor ($136,000) is above 36% of the 2,096 Engineering (non-software) roles in California listed on this site; 21 others list the same floor. Their median floor is $146,200; the middle half runs from $124,000 to $174,250.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 7, 2026.
This listingSenior ASIC Design Engineer - Memory Subsystem$136,000 to $264,500
Public Sector Program Support$136K to $276K
Senior Package Layout Engineer - Hardware$136,000 to $258,750
Senior RMA Customer Experience Manager$136,000 to $212,750
Go-to-Market Product Manager$136,000 to $258,750
Senior PR Manager, Datacenter Architecture$136,000 to $270,250
Senior Technical Program Manager - Tegra$136K to $276K
Chart as a table
| Role | Published base |
|---|---|
| Senior ASIC Design Engineer - Memory Subsystem (this listing) | $136,000 - $264,500 |
| Public Sector Program Support | $136K - $276K |
| Senior Package Layout Engineer - Hardware | $136,000 - $258,750 |
| Senior RMA Customer Experience Manager | $136,000 - $212,750 |
| Go-to-Market Product Manager | $136,000 - $258,750 |
| Senior PR Manager, Datacenter Architecture | $136,000 - $270,250 |
| Senior Technical Program Manager - Tegra | $136K - $276K |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-10-30
Where this pay comes from
Location as the employer wrote it: US, CA, Santa Clara (Levels 3-4 combined)
136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
