Senior Circuit Design Engineer
Company websitenvidia.com (NVIDIA, opens in new tab)
Base salary $136,000 to $264,500
Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSanta Clara, CA
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (3 min ago) · observed since
About this job
We are now hiring for a Senior Circuit Design Engineer for Standard Cell and/or ROM.
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 30 years. It’s an unique legacy of innovation that’s fueled by great technology—and amazing people. NVIDIA's invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing — with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. Today, we are increasingly known as “the AI computing company”. We are looking to grow our company and teams with the smartest people in the world. We're rapidly growing our research and development for Inference. We specialize in developing GPU-accelerated Deep Learning software. Researchers around the world are using NVIDIA GPUs to power a revolution in Deep Learning and enabling breakthroughs in numerous areas.
What you will be doing:
Work on the cutting edge standard cell libraries and/or custom ROM (Read Only Memory) modules in deep submicron technologies.
Drive the concepts of the transistor level standard cell circuit design, modeling and performance analysis process.
Lead the function/feasibility verification of new ROM designs and the setup of new design flows.
Provide creative new insights to support existing tools and flows and develop new simulations to perform design margin evaluations.
Collaborate with cross function teams with regards to standard cell design improvement opportunities. We will improve on our quality checks on the libraries.
What we need to see:
MS in Electrical or Computer Engineering (or equivalent experience).
5+ years of experience is preferred.
We are looking for strong background in deep submicron process issues.
Deep understanding of the design and verification of standard cell libraries and/or custom ROMs.
Hands-on experience running SPICE simulation, and capability to adapt to new simulation tools.
Experience with running EM/IR, aging, noise, margin, and high sigma variation simulations.
Experiences working with mask designers on layouts. Hands-on experience of DRC/LVS debug.
Experience of designing flip flops, level shifters, math cells and/or custom ROMs, register files, SRAM.
Strong proficiency in scripting language, such as, Perl, Tcl, Make, and automation methods/algorithms a certain plus.
Excellent teamwork, communication and analytical skills.
136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.Source: NVIDIA on Workday · View original posting (opens in new tab)
This listingSenior Circuit Design Engineer$136,000 to $264,500
Public Sector Program Support$136K to $276K
Senior Package Layout Engineer - Hardware$136,000 to $258,750
Senior RMA Customer Experience Manager$136,000 to $212,750
Go-to-Market Product Manager$136,000 to $258,750
Senior PR Manager, Datacenter Architecture$136,000 to $270,250
Senior Technical Program Manager - Tegra$136K to $276K
Chart as a table
| Role | Published base |
|---|---|
| Senior Circuit Design Engineer (this listing) | $136,000 - $264,500 |
| Public Sector Program Support | $136K - $276K |
| Senior Package Layout Engineer - Hardware | $136,000 - $258,750 |
| Senior RMA Customer Experience Manager | $136,000 - $212,750 |
| Go-to-Market Product Manager | $136,000 - $258,750 |
| Senior PR Manager, Datacenter Architecture | $136,000 - $270,250 |
| Senior Technical Program Manager - Tegra | $136K - $276K |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-10-30
Where this pay comes from
Location as the employer wrote it: US, CA, Santa Clara (Levels 3-4 combined)
136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
