Senior Silicon Circuit Validation Engineer

NVIDIA's chips define the ceiling of what silicon can do. But raw performance is only part of the story. The circuits that make a product trustworthy — the ones that enforce security boundaries, catch failures before they propagate, extend silicon lifetime under the hardest workloads, and unlock the last margin of performance safely — these are the circuits that determine whether a product ships or stalls, earns trust or loses it. This role co-designs them. The Silicon Co-Design Group owns the boundary between design intent and silicon reality. When a product ships at frequency, at quality, and with the reliability the world's AI infrastructure demands, this team is a reason why.

You will be the engineer who knows what these circuits are actually doing. Safety, security, reliability, and performance enhancement features are not decorative. They sit on the critical path of every product decision — binning, guard-banding, sign-off, field quality. When one of them doesn't behave the way the model predicted, the consequences reach further than a single block. You find out why. You close the gap between design intent and silicon reality, and your data is what architecture, circuit design, and product teams act on. The engineers who do this well don't just measure circuits — they understand them deeply enough to know what a deviation means before anyone else does. They think like circuit designers, work like experimentalists, and reason like data scientists. If that describes you, read on.

What you'll be doing:

• Own the co-design, bring-up, and post-silicon validation of the analog, digital, and mixed-signal circuits that underpin NVIDIA's safety, security, reliability, and performance enhancement features — across the full PVT space, from first power-on through production sign-off.

• Close the simulation-to-silicon gap. Build methodologies that correlate measured circuit behavior against pre-silicon predictions, quantify where the model diverges from reality, and produce analysis that design and architecture teams can act on with confidence.

• Trace failures to their source — a circuit marginality, a power integrity interaction, a process corner the model didn't anticipate, or a system-level coupling — and drive the resolution all the way through to confirmation.

• Own and build AI agents that work at your direction: automated test orchestration, intelligent data pipelines, and analysis flows that expand coverage and compress cycle time without sacrificing rigor. Know where AI accelerates real work and where it introduces risk.

• Build the tools your work depends on. Design and own automation and analysis infrastructure that lets you execute efficiently across multiple products simultaneously without sacrificing depth or coverage.

• Sit at the decision table. Your data drives binning strategy, guard-band decisions, reliability sign-off, and design improvements for future programs. When the data is ambiguous, your analysis is what resolves it.

• Lead and mentor junior engineers and interns. Raise the technical floor of the team around you.

What we need to see:

• BS or MS in Electrical Engineering, Computer Engineering, or equivalent experience in the lab.

• 8+ years of hands-on silicon bring-up, frequency and power characterization, or post-silicon validation on real hardware.

• Strong circuit fundamentals — analog, digital, and mixed-signal — with the intuition to know what you're measuring and why it matters.

• Hands-on lab depth: oscilloscopes, multimeters, DAQs, spectrum analyzers, and silicon debug tools. Comfort with tester-to-system correlation.

• Depth in product binning, PVT analysis, guard-banding, and optimization trade-offs. Enough statistical fluency to know when a distribution is telling you something.

• Exposure to critical path analysis, power integrity, dI/dt and PDN analysis, transistor physics, and silicon reliability and aging mechanisms.

• Scripting proficiency in Python, C/C++, or equivalent. You build the infrastructure your characterization depends on.

Ways to stand out from the crowd:

• You've built a co-design or correlation methodology precise enough that other teams adopted it.

• Traced a silicon anomaly — a noise issue, a margin failure, a feature that didn't hold across corners — to its root cause and driven the fix all the way through to closure.

• Built or deployed AI-driven flows for circuit analysis or failure triage, and can speak to both the outcome and the guardrails you put in place.

• Led or mentored engineers and made them measurably better at the craft.

• Experience on datacenter-scale or high-performance silicon, where complexity raises the cost of being wrong and the standard for rigor is correspondingly higher.

The circuits you co-design don't just enhance performance — they define whether the product is safe, secure, and reliable enough to ship. When they work, the product earns trust at scale. When they don't, everything downstream is at risk. If that is the kind of problem you want to own, we want to hear from you.

Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary range for this position is 168,000 USD – 264,500 USD.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 3, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.