Sr. Staff Power Performance Architect
Company websited-matrix.ai (d-Matrix, opens in new tab)
Base salary $165K to $265K
Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSanta Clara, CA
- WorkplaceHybrid
- Status at last checkSource accepting applications when checked
- Last checked (2 h ago) · observed since
About this job
Join d-Matrix and help build the future of AI inference. We’ve pioneered a memory-centric architecture that brings compute directly into memory, making AI faster, more energy efficient, and accessible on a global scale. From chips and software to rack-scale systems, our team is tackling some of AI infrastructure’s hardest challenges — and shipping breakthrough technology today. If you want to create what comes next and help make infinite inference possible, we’d love to hear from you.
Our culture is built on respect, collaboration, and direct communication. We value humility, we believe our different perspectives lead to better solutions, and we’re looking for people who are driven by execution and energized by hard problems.
Role Overview
d-Matrix is looking for a Senior Staff Power Performance Architect to own pre-silicon power estimation across our next-generation AI accelerators. In this role, you will drive both RTL-level and physical-design-level power estimation, and build an architectural power estimation tool that models power from system configuration and die-level metrics for AI workloads. You will partner closely with front-end architects, DV engineers, and backend design teams to identify power activity windows, define performance monitoring requirements, and translate that analysis into hardware capability improvements and die-level design changes. This role also contributes directly to micro-architecture and RTL design, verification, and silicon bring-up, making it central to how d-Matrix balances performance and power efficiency at the silicon level.
What You Will Do
Own pre-silicon power estimation for design blocks, spanning both RTL-level and physical-design-level estimation.
Partner with front-end and DV engineers to identify power activity windows, and work with the RTL team to implement estimation feedback and optimize power.
Build an architectural power estimation tool for AI workloads that computes power from system configuration and die-level metrics, including workload profiling based on memory size, bandwidth, and gate counts of compute/memory blocks.
Collaborate with frontend architects and backend design to define performance monitor availability, system requirements, and usage, then drive that analysis into hardware capability improvements and die-level design modifications.
Lead micro-architecture and RTL design, synthesis, and logic/physical power-performance verification using leading-edge CAD tools and semiconductor process technologies.
Design and implement performance-enabling and power-saving/monitoring functions that support efficient design, test, and debug, and participate in silicon bring-up and validation.
What You Will Bring
8+ years of relevant experience in IC power/performance architecture, RTL, or physical design, with a Master's degree in Electrical Engineering, Computer Engineering, or Computer Science.
Solid understanding of power, performance, micro-architecture, RTL, and physical design in the context of digital system and IC design, including the full IC design flow (Arch → uarch → RTL → Schematic → Layout → Verification → Fabrication → HVM).
Familiarity with at least one EDA tool for power estimation.
Ability to move fluidly between RTL, physical design, and automation, including building script utilities to improve design execution productivity across the design team.
Programming proficiency in TCL and Python, with experience using libraries, APIs, data parsing, and algorithmic thinking.
Self-motivated with a fast, iterative approach to design work, sound engineering judgment, and a bias toward action.
Preferred Qualifications
Exposure to power estimation and performance metrics such as TDP, PMAX, EDP, Peak, and Average.
Familiarity with power/frequency scaling techniques (DFS, DVFS, AFS, AVFS).
Familiarity with power delivery network (PDN) analysis, including resonance, impedance (Z(f)), and voltage droop analysis.
Equal Opportunity Employment Policy
d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication, and a willingness to embrace challenges and learn together every day.
d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individuals interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of all applicants. Thank you for your understanding and cooperation.
Source: d-Matrix on Ashby · View original posting (opens in new tab)
Pay in context
This role's base floor ($165,000) is above 66% of the 2,072 Engineering (non-software) roles in California listed on this site; 26 others list the same floor. Their median floor is $146,500; the middle half runs from $125,000 to $175,000.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 6, 2026.
This listingSr. Staff Power Performance Architect$165K to $265K
Sr Staff Site Reliability Engineer, AI Infrastructure$175K to $265K
Staff Analog Design Engineer, SerDes Clocking$155K to $250K
Sr. Staff Thermal Design Engineer$175K to $265K
Senior Manager, Information Security$175K to $265K
Sr. Staff PCB Design Engineer$175K to $265K
Staff Analog Design Engineer, TX/RX Datapath$155K to $250K
Chart as a table
| Role | Published base |
|---|---|
| Sr. Staff Power Performance Architect (this listing) | $165K - $265K |
| Sr Staff Site Reliability Engineer, AI Infrastructure | $175K - $265K |
| Staff Analog Design Engineer, SerDes Clocking | $155K - $250K |
| Sr. Staff Thermal Design Engineer | $175K - $265K |
| Senior Manager, Information Security | $175K - $265K |
| Sr. Staff PCB Design Engineer | $175K - $265K |
| Staff Analog Design Engineer, TX/RX Datapath | $155K - $250K |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-09-13
Where this pay comes from
Location as the employer wrote it: Santa Clara
USD 165,000 – 265,000 · 1 YEAR · Salary
- Method
- Structured pay field published by the employer
- Checked
- Rule set
- us-base-v2
The employer's job board publishes this pay as a dedicated data field. We read the field directly; no interpretation was needed.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
