Hardware Test Engineer
Company websitedensityai.com (DensityAI, opens in new tab)
Base salary $145K to $220K
Employer-published annual base salary, USD. Advertised base range in Mountain View, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationMountain View, CA
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (26 min ago) · observed since
About this job
About the role:
Own the test that proves our AI accelerator hardware works — from the packaged units, to the boards they sit on, to the systems they ship in. You'll develop the test setups, test hardware, and coverage/yield/throughput that let us catch problems early and ship at volume. You'll sit at the seam between silicon/packaging and the systems our accelerators run in, and own the test strategy that spans package level, board level, and — increasingly — full system level.
What you'll do
- Develop and run package-level test — socket-based bring-up and validation of packaged units: power-up, interface/interconnect continuity, and functional/parametric checks against spec (board↔package interface, not ATE silicon device test)
- Develop and run board-level test — functional, structural (boundary scan/JTAG), in-circuit, and bring-up validation for accelerator boards and system hardware
- Build out system-level test — bring up and validate assembled accelerator systems against spec, including functional, stress, and burn-in flows
- Design and validate test hardware and fixtures — sockets, connectors, load boards, and board/system fixtures for high-speed and high-current test
- Drive test coverage, yield analysis, and test-time/cost reduction across the product lifecycle
- Lead new-product test bring-up; resolve test escapes, yield excursions, and hardware failures with data-driven root cause
- Run characterization and correlation across levels — package ↔ board ↔ system, and bench ↔ production test
- Define test specs, limits, and guardbands with design, product, packaging, and reliability engineering
- Transfer and sustain test programs at OSAT/CM and manufacturing partners through ramp to high volume
- Use and develop AI-assisted tool flows to accelerate test development, debug, and yield analysis
What we're looking for
- BS/MS in Electrical/Computer Engineering or equivalent plus 5+ years in package/board/system-level hardware test engineering
- Hands-on test experience across at least two of package-level, board-level, and system-level test — with the ability to own the others
- Package and board test hardware experience (sockets, connectors, load boards, fixtures) and the signal/power integrity that comes with high-speed, high-current test
- Lab bring-up and debug skills: oscilloscopes, logic and protocol analyzers, power and thermal instrumentation
- Data analysis and statistical skills for yield, characterization, and correlation work
- (Optional) High-speed I/O / SerDes, DDR/HBM, RF, or high-current/power-device test; structural test (boundary scan); scripting/automation (Python, C++); system burn-in and reliability test; OSAT/CM partner management
Compensation
Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.
Visa Sponsorship
DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.
Export Controls
Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.
Equal Opportunity
DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.
Full compensation packages are based on candidate experience and relevant certifications.
California pay range
$145,000—$220,000 USD
Compensation
Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.
Visa Sponsorship
DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.
Export Controls
Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.
Equal Opportunity
DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.
Source: DensityAI on Greenhouse · View original posting (opens in new tab)
Pay in context
This role's base floor ($145,000) is above 45% of the 2,084 Engineering (non-software) roles in California listed on this site; 24 others list the same floor. Their median floor is $146,200; the middle half runs from $124,943 to $173,250.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 7, 2026.
This listingHardware Test Engineer$145K to $220K
PCB Layout Engineer$150K to $215K
Hardware Reliability Engineer$132K to $220K
Package Layout Engineer$165K to $225K
Silicon Supply Chain$168K to $250K
Mechanical Engineer, Systems$170K to $260K
AI Core DV Engineer$180K to $275K
Chart as a table
| Role | Published base |
|---|---|
| Hardware Test Engineer (this listing) | $145K - $220K |
| PCB Layout Engineer | $150K - $215K |
| Hardware Reliability Engineer | $132K - $220K |
| Package Layout Engineer | $165K - $225K |
| Silicon Supply Chain | $168K - $250K |
| Mechanical Engineer, Systems | $170K - $260K |
| AI Core DV Engineer | $180K - $275K |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-06-18
Where this pay comes from
Location as the employer wrote it: Mountain View, CA
$145,000—$220,000 USD
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
