Senior ASIC Verification Engineer
Company websitenvidia.com (NVIDIA, opens in new tab)
Base salary $136,000 to $264,500
Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA +2 more
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSanta Clara, CA +2 more
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (16 min ago) · observed since
All places named
- Santa Clara, CA
- Austin, TX
- Durham, NC
About this job
NVIDIA is seeking elite ASIC Verification Engineers to verify the design and implementation of the world’s leading GPUs. This position offers the opportunity to have real impact in a dynamic and technology-focused company, with your work influencing product lines ranging from consumer graphics to artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
In this position, you will help to build the high-performance processor elements that implement programmable compute and graphics functionality.
What you'll be doing:
As a key member of our ASIC Verification team, you will:
- Verify the design and implementation of the industry's leading GPUs.
- Be responsible for verification of the ASIC design, architecture, golden models, and micro-architecture using advanced verification methodologies such as UVM or equivalent experience.
- Understand the design and implementation of your unit, define the verification scope, develop the verification infrastructure, and verify the correctness of the design.
- Collaborate with architects, designers, and pre-/post-silicon verification teams to accomplish your tasks.
What we need to see:
- Bachelor’s Degree in EE, CS, or CE; or equivalent experience.
- 5+ years of relevant experience.
- Background in verification using random stimulus, along with functional coverage and assertion-based verification methodologies.
- Experience with design and verification tools (VCS or equivalent simulation tools; debug tools like Debussy, GDB).
- Experience in crafting test bench environments for unit- and system-level verification.
- Expertise in SystemVerilog or similar HVL.
- C++ programming language experience, including a strong understanding of object-oriented programming principles, data structures, and algorithms.
- Good working knowledge of the fundamentals of computer architecture and digital design.
- Excellent debugging and analytical skills.
- Prior experience with processor pipeline verification is desirable.
#LI-Hybrid
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.Source: NVIDIA on Workday · View original posting (opens in new tab)
Pay in context
This role's base floor ($136,000) is above 36% of the 2,087 Engineering (non-software) roles in California listed on this site; 21 others list the same floor. Their median floor is $146,200; the middle half runs from $124,886 to $173,000.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 7, 2026.
This listingSenior ASIC Verification Engineer$136,000 to $264,500
Public Sector Program Support$136K to $276K
Senior Package Layout Engineer - Hardware$136,000 to $258,750
Senior RMA Customer Experience Manager$136,000 to $212,750
Go-to-Market Product Manager$136,000 to $258,750
Senior PR Manager, Datacenter Architecture$136,000 to $270,250
Senior Technical Program Manager - Tegra$136K to $276K
Chart as a table
| Role | Published base |
|---|---|
| Senior ASIC Verification Engineer (this listing) | $136,000 - $264,500 |
| Public Sector Program Support | $136K - $276K |
| Senior Package Layout Engineer - Hardware | $136,000 - $258,750 |
| Senior RMA Customer Experience Manager | $136,000 - $212,750 |
| Go-to-Market Product Manager | $136,000 - $258,750 |
| Senior PR Manager, Datacenter Architecture | $136,000 - $270,250 |
| Senior Technical Program Manager - Tegra | $136K - $276K |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-10-30
Where this pay comes from
Location as the employer wrote it: US, CA, Santa Clara • US, TX, Austin • US, NC, Durham (Levels 3-4 combined)
136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
