Six Figure Work

Senior DFT Engineer

NVIDIA

Company websitenvidia.com (NVIDIA, opens in new tab)

Base salary $136,000  to $264,500

Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA

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  • LocationSanta Clara, CA
  • WorkplaceWorkplace not stated
  • Status at last checkSource accepting applications when checked
  • Last checked (1 h ago) · observed since

About this job

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work , to amplify human imagination and intelligence.  Make the choice to join us today.

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.

What you'll be doing:

  • As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.

  • In addition, you will help develop and deploy DFT methodologies for our next generation products.

  • You will also help mentor junior engineers on test designs and trade-offs including cost and quality.

What we need to see:

  • BSEE (or equivalent experience) with 5+, MSEE with 3+ years of experience or PhD in DFT or related domains

  • Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation

  • Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools

  • Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs

  • Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development

  • Strong programming and scripting skills in Perl, Python or Tcl desired

  • Extraordinary written and oral communication skills with the curiosity to work on rare challenges

Our technology has no boundaries! NVIDIA is building the world’s most groundbreaking and state of the art compute platforms for the world to use. It’s because of our work that scientists, researchers and engineers can advance their ideas.  At its core, our visual computing technology not only enables an outstanding computing experience, but it is also energy efficient!  We pioneered a supercharged form of computing loved by the most demanding computer users in the world - scientists, designers, artists, and gamers.

NVIDIA offers highly competitive salaries and a comprehensive benefits package. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to hear from you!

#LI-Hybrid

Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:
136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 3, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Source: NVIDIA on Workday · View original posting (opens in new tab)

This range next to 6 other live NVIDIA roles with the nearest advertised base floor
Chart as a table
This range next to 6 other live NVIDIA roles with the nearest advertised base floor
RolePublished base
Senior DFT Engineer (this listing)$136,000 - $264,500
Public Sector Program Support$136K - $276K
Senior Package Layout Engineer - Hardware$136,000 - $258,750
Senior RMA Customer Experience Manager$136,000 - $212,750
Go-to-Market Product Manager$136,000 - $258,750
Senior PR Manager, Datacenter Architecture$136,000 - $270,250
Senior Technical Program Manager - Tegra$136K - $276K

Same $100K to $400K scale as every card. All NVIDIA roles · How to read the bar

Observed changes

  1. First observed on the employer's board
  2. Began meeting the published-salary criteria
Observed since
Employer-stated posting date
2026-10-30
Where this pay comes from

Location as the employer wrote it: US, CA, Santa Clara (Levels 3-4 combined)

136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.

Method
Employer text, read with fixed rules and re-verified
Checked
Rule set
us-base-v2

The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.

What we verified

  • The pay figures come from the employer's own listing, quoted exactly above.
  • The pay is an annual base salary in US dollars with a minimum of at least $100,000.
  • The role was publicly listed on the employer's job board when last checked.

We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.