Senior Manager, Post-Silicon Bring-Up
Company websitenvidia.com (NVIDIA, opens in new tab)
Base salary $232K to $368K
Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSanta Clara, CA
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (13 min ago) · observed since
About this job
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
We are seeking a Senior Manager to lead post-silicon bring-up and productization for complex, high-performance silicon products, driving execution from first power-on through debug, validation, production readiness, and sustained product ramp. This role is ideal for a leader who combines deep technical judgment with strong multi-functional execution and can establish the operating rhythm required to move silicon from early lab readiness to high-volume production. The scope includes setting operational objectives, leading significant portions of large programs, influencing through deep expertise, and managing across teams and technical specialty areas.
What You’ll Be Doing:
Lead the end-to-end post-silicon execution plan, from first-silicon power-on through production qualification and volume ramp.
Drive technical and program execution across architecture, design, verification, firmware, software, boards, systems, test, product engineering, and operations to achieve bring-up, debug, validation, and productization achievements.
Lead the bring-up operating model, including priorities, staffing, customer concern paths, execution reviews, issue triage, metrics, and closure plans for the highest-risk silicon issues.
Lead the resolution of sophisticated post-silicon issues involving power, clocks, reset, boot, interfaces, performance, reliability, and coordination between hardware components and software systems, ensuring rapid root-cause analysis and effective cross-team closure.
Drive silicon characterization and reliability qualification plans through execution. This involves assessments of electrical, speed, power, thermal, environmental, and operational conditions. It also includes customer-sampling, production-release criteria, and automotive qualification flows like AEC-Q100, when applicable.
Establish and continuously improve bring-up methodology, test planning, debug readiness, lab readiness, and execution processes to increase speed, quality, and predictability across programs.
Partner with senior leadership to communicate readiness, risks, dependencies, and recovery plans, and drive decisions that balance schedule, quality, and production objectives.
Help shape the broader post-silicon roadmap by applying bring-up findings to design, verification, debug architecture, and productization flows.
What We Need to See:
BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
12+ overall years of proven experience and 5+ years of management experience, including significant leadership in post-silicon bring-up, validation, debug, or productization for complex SoCs, GPUs, ASICs, or systems.
Proven experience leading teams through first-silicon bring-up, issue triage, debug closure, and transition to production.
Deep technical understanding of digital design, computer or system architecture, power, timing, clocking, reset, noise, fault analysis, and hardware-software interactions.
Strong experience with post-silicon debug and validation flows, including lab execution, test planning, data-driven issue management, and multi-functional execution in fast-moving environments.
Familiarity with driving silicon characterization and reliability qualification, including electrical and process-voltage-temperature characterization, HTOL, ELFR, package qualification, and AEC-Q100 for automotive programs, where applicable.
Demonstrated ability to work effectively across pre-silicon and post-silicon teams, influence senior partners, and drive decisions across organizational boundaries.
Strong communication and interpersonal skills, with the ability to simplify uncertainty, create structure, and keep teams aligned under aggressive schedules.
Ways to Stand Out from the Crowd:
Experience leading bring-up for both SoC- and GPU-class silicon or highly integrated platform programs.
Hands-on experience with first power-on, system bring-up, silicon characterization, binning, reliability qualification, or production ramp is a plus!
Experience building bring-up methodologies, debug infrastructure, or validation frameworks that improved execution quality across multiple product generations.
Strong background in firmware, low-level software, or hardware-software co-debug for complex systems.
Experience driving pre-silicon execution, including multi-functional planning and execution through design, verification, and tapeout readiness, is a strong plus.
Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary range for this position is 232,000 USD – 368,000 USD.You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.Source: NVIDIA on Workday · View original posting (opens in new tab)
This listingSenior Manager, Post-Silicon Bring-Up$232K to $368K
Senior Manager, ASIC Chip Engineering$232K to $368K
Principal Chip Lead, Silicon Co-Design Group$232K to $368K
Principal System Power Management and Performance Architect$232K to $368K
Director, Global Workplace Design$232,000 to $356,500
Principal EDA R&D Engineer$232K to $368K
Principal Photonics IC Design Engineer$232K to $368K
Chart as a table
| Role | Published base |
|---|---|
| Senior Manager, Post-Silicon Bring-Up (this listing) | $232K - $368K |
| Senior Manager, ASIC Chip Engineering | $232K - $368K |
| Principal Chip Lead, Silicon Co-Design Group | $232K - $368K |
| Principal System Power Management and Performance Architect | $232K - $368K |
| Director, Global Workplace Design | $232,000 - $356,500 |
| Principal EDA R&D Engineer | $232K - $368K |
| Principal Photonics IC Design Engineer | $232K - $368K |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-10-30
Where this pay comes from
Location as the employer wrote it: US, CA, Santa Clara
base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary range for this position is 232,000 USD – 368,000 USD.
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
