Senior Mixed Signal Design Engineer
Company websitenvidia.com (NVIDIA, opens in new tab)
Base salary $196K to $368K
Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSanta Clara, CA
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (53 min ago) · observed since
About this job
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice and join us today!
This is a diverse team working with innovative, ground breaking technology. If you are someone that loves a challenge, come join this complementary team and help move the needle! As a member of our Mixed Signal team, you will lead the design of CMOS high-speed interface circuits and mixed-signal circuits. Strong hands-on experience in the lab with silicon validation, debugging, characterization and bring up.
What you'll be doing:
Lead design and implementation of high speed interface circuit
Design projects include high speed transceivers and high frequency PLLs
Design, simulation, and verification of mixed-signal circuits
Supervise closely IC circuit/mask designers, provide floorplan and layout guidelines
Support lab characterization of silicon
Tackle challenges of circuit design in deep submicron CMOS
Take designs through implementation and productization
Work with multi-functional teams
What we need to see:
MS in Electrical Engineering or equivalent experience
4+ years of design experience in CMOS analog / mixed-signal circuit Design
Solid understanding of Cadence custom design tools, circuit simulator, timing analysis tool
A great teammate with good interpersonal skills
Proven experience in crafting and mentoring designers
Extensive experience in Tx, Rx, CDR, PLL for high speed IO interfaces
In-depth understanding of deep submicron CMOS process and related circuit design issues
Experience in silicon bring-up, debugging and use of lab instrumentation is required
Knowledge in system level timing budget, signal integrity, and power integrity is a plus
Experience in Verilog, Matlab, Primetime, Nanotime
196,000 USD – 310,500 USD for Level 5; and 232,000 USD – 368,000 USD for Level 6.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.Source: NVIDIA on Workday · View original posting (opens in new tab)
This listingSenior Mixed Signal Design Engineer$196K to $368K
Senior System Integration Engineer, Memory$196,000 to $310,500
Senior FPGA Prototyping Engineer - Hardware$196K to $368K
Senior ASIC Floorplan Design Engineer$196,000 to $310,500
Senior SRAM Engineer$196,000 to $310,500
Senior Manager, PR - AI Software$196,000 to $310,500
Manager, ASIC Chip - GPU$196,000 to $310,500
Chart as a table
| Role | Published base |
|---|---|
| Senior Mixed Signal Design Engineer (this listing) | $196K - $368K |
| Senior System Integration Engineer, Memory | $196,000 - $310,500 |
| Senior FPGA Prototyping Engineer - Hardware | $196K - $368K |
| Senior ASIC Floorplan Design Engineer | $196,000 - $310,500 |
| Senior SRAM Engineer | $196,000 - $310,500 |
| Senior Manager, PR - AI Software | $196,000 - $310,500 |
| Manager, ASIC Chip - GPU | $196,000 - $310,500 |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-10-30
Where this pay comes from
Location as the employer wrote it: US, CA, Santa Clara (Levels 5-6 combined)
196,000 USD – 310,500 USD for Level 5; and 232,000 USD – 368,000 USD for Level 6.
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
