Six Figure Work

Staff Analog Design Engineer

d-Matrix

Company websited-matrix.ai (d-Matrix, opens in new tab)

Base salary $155K  to $250K

Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA

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  • LocationSanta Clara, CA
  • WorkplaceHybrid
  • Status at last checkSource accepting applications when checked
  • Last checked (1 h ago) · observed since

About this job

Join d-Matrix and help build the future of AI inference. We’ve pioneered a memory-centric architecture that brings compute directly into memory, making AI faster, more energy efficient, and accessible on a global scale. From chips and software to rack-scale systems, our team is tackling some of AI infrastructure’s hardest challenges — and shipping breakthrough technology today. If you want to create what comes next and help make infinite inference possible, we’d love to hear from you.

Our culture is built on respect, collaboration, and direct communication. We value humility, we believe our different perspectives lead to better solutions, and we’re looking for people who are driven by execution and energized by hard problems.

Role Overview

d-Matrix is looking for a Staff Analog Design Engineer to lead analog-mixed signal IC design for our next-generation AI inference accelerators. This role owns circuit design for two critical subsystems: our in-memory-compute engine and the die-to-die serial interface that enables scale-out. You will drive design from schematic through silicon bring-up, guiding layout engineers working in deep sub-micron process nodes (7nm and below) and ensuring designs meet low-power performance targets across process-voltage-temperature corners. You will partner closely with layout engineers, backend/digital integration teams, and cross-site colleagues to deliver silicon-ready designs. This is a high-impact role for someone who wants to shape the analog foundations of state-of-the-art AI hardware.

What You Will Do

  • Design analog-mixed signal circuits using industry-standard tools such as Cadence and Synopsys

  • Develop schematic-level circuit designs and conduct system-level performance analysis

  • Build test benches to support simulation and verification, including Monte Carlo yield analysis across PVT corners

  • Guide layout engineers on circuit layout in deep sub-micron process nodes (7nm and below), including hands-on minor layout adjustments as needed

  • Partner with backend engineers to integrate design and layout, and provide circuit models to support backend verification

  • Support testboard design for silicon bring-up, bench debug, and characterization

  • Build scripts to support silicon bring-up and test feature validation

What You Will Bring

  • BS, MS, or PhD in Electrical Engineering with 5+ years of related professional experience in high-speed circuit design (e.g., phase interpolators, clocking, PLL design)

  • Experience with schematic capture, SPICE simulation, and Monte Carlo simulation

  • Experience with circuit layout, extraction, and back-annotated simulation

  • Experience with channel modeling using MATLAB or similar tools

  • Strong cross-functional communication and collaboration skills, with the ability to work effectively across distributed, cross-site teams

  • Strong analytical and problem-solving skills, with the ability to manage multiple priorities in a fast-paced environment

Preferred Qualifications

We'd be excited about candidates with deep expertise in any one of the following areas:

  • SerDes verification & characterization — building/maintaining analog verification infrastructure (testbenches, regressions, Monte Carlo campaigns), migrating blocks across process nodes, or reliability analysis (EM, IR drop, ESD/latch-up)

  • Clocking & CDR — ownership of a low-jitter PLL, phase interpolator, or CDR loop through silicon at 25 Gbps+ per lane, including bang-bang/baud-rate/DSP-assisted CDR architectures

  • TX/RX datapath — high-speed driver or receive front-end design (CTLE, VGA, samplers), DFE/FFE equalization, or PAM4/DSP-based receiver architectures

  • Die-to-die interconnect experience (UCIe, BoW, or proprietary D2D PHY), familiarity with relevant specs (OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/7), or standards body participation

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication, and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individuals interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of all applicants. Thank you for your understanding and cooperation.

Source: d-Matrix on Ashby · View original posting (opens in new tab)

Pay in context

This role's base floor ($155,000) is above 61% of the 2,036 Engineering (non-software) roles in California listed on this site; 5 others list the same floor. Their median floor is $146,100; the middle half runs from $124,000 to $173,000.

Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 6, 2026.

This range next to 6 other live d-Matrix roles with the nearest advertised base floor
Chart as a table
This range next to 6 other live d-Matrix roles with the nearest advertised base floor
RolePublished base
Staff Analog Design Engineer (this listing)$155K - $250K
Staff Analog Design Engineer, SerDes Clocking$155K - $250K
Staff Analog Design Engineer, TX/RX Datapath$155K - $250K
Staff Software Engineer, Developer Automation$155K - $235K
Staff Test & Release Engineer, Inference Cloud$155K - $235K
Staff Software Engineer, Developer Automation - Bazel$155K - $235K
Sr. Staff Power Performance Architect$165K - $265K

Same $100K to $400K scale as every card. All d-Matrix roles · How to read the bar

Observed changes

  1. First observed on the employer's board
  2. Began meeting the published-salary criteria
Observed since
Employer-stated posting date
2025-05-20
Where this pay comes from

Location as the employer wrote it: Santa Clara

USD 155,000 – 250,000 · 1 YEAR · Salary

Method
Structured pay field published by the employer
Checked
Rule set
us-base-v2

The employer's job board publishes this pay as a dedicated data field. We read the field directly; no interpretation was needed.

What we verified

  • The pay figures come from the employer's own listing, quoted exactly above.
  • The pay is an annual base salary in US dollars with a minimum of at least $100,000.
  • The role was publicly listed on the employer's job board when last checked.

We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.