Manager, Digital Design - Mixed-Signal High-Speed I/O SerDes
Company websitenvidia.com (NVIDIA, opens in new tab)
Base salary $196,000 to $310,500
Employer-published annual base salary, USD. Advertised base range in Santa Clara, CA
You apply on the employer's own site. Six Figure Work does not handle applications.
- LocationSanta Clara, CA
- WorkplaceWorkplace not stated
- Status at last checkSource accepting applications when checked
- Last checked (1 h ago) · observed since
About this job
Are you looking for a Digital Design Manager role? As a Senior Digital Design Manager in our Mixed-Signal High-Speed I/O SerDes group, you'll lead a team working on NVIDIA's latest groundbreaking technology that enables and accelerates gaming, artificial intelligence, deep learning, and autonomous driving. Your team's designs will be consumed by standard as well as industry-leading proprietary high-speed protocols, serving as key IPs in sophisticated SoCs. You'll collaborate closely with analog designers, system architects, and other engineering teams to drive innovation and deliver high-performance solutions.
What you'll be doing:
Lead and mentor a team of engineers in developing mixed-signal chips
Supervise the planning and specification of algorithms, evaluating PPA (Power, Performance, Area) trade-offs
Guide the design of digital circuits such as filters and analog calibration circuits
Ensure verification of digital designs using direct and random testing methodologies
Lead front-end design flows (Lint/CDC/Synthesis/DFT/LEC/STA) and coordinate with back-end teams for successful chip tape-outs
Drive silicon bring-up efforts and performance optimization
Collaborate with multi-functional teams to align technology roadmaps with business objectives
Establish and maintain standard methodologies for mixed-signal design and verification
What we need to see:
M.S. or Ph.D. in Electrical Engineering or equivalent experience and over 8 years of overall experience in mixed signal
Proven experience in mixed-signal chip design, with 3+ years in a leadership role
Expertise in Verilog or SystemVerilog, logic design, and circuit modeling in RTL for mixed-signal blocks
Strong background in custom digital circuit design and adaptation algorithms (FFE, DFE, CTLE, CDR, offset cancellation), understanding of high-speed SerDes I/O digital design, with knowledge of protocols like Ethernet and PCIe
Experience with industry-standard verification methodologies, such as UVM
Proficiency with static timing and formal verification tools
Excellent communication and leadership skills, with the ability to drive technical strategy
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice and join us today!
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary range for this position is 196,000 USD – 310,500 USD.You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.Source: NVIDIA on Workday · View original posting (opens in new tab)
Pay in context
This role's base floor ($196,000) is above 85% of the 3,582 Engineering (non-software) roles in California listed on this site; 20 others list the same floor. Their median floor is $147,000; the middle half runs from $125,000 to $173,000.
Only jobs on this site count, and each one publishes a base salary of $100,000 or more, so this compares six-figure jobs with each other, not with the whole market. Computed Nov 8, 2026.
This listingManager, Digital Design - Mixed-Signal High-Speed I/O SerDes$196,000 to $310,500
Senior Mixed Signal Design Engineer$196K to $368K
Senior System Integration Engineer, Memory$196,000 to $310,500
Senior FPGA Prototyping Engineer - Hardware$196K to $368K
Senior ASIC Floorplan Design Engineer$196,000 to $310,500
Senior SRAM Engineer$196,000 to $310,500
Senior Manager, PR - AI Software$196,000 to $310,500
Chart as a table
| Role | Published base |
|---|---|
| Manager, Digital Design - Mixed-Signal High-Speed I/O SerDes (this listing) | $196,000 - $310,500 |
| Senior Mixed Signal Design Engineer | $196K - $368K |
| Senior System Integration Engineer, Memory | $196,000 - $310,500 |
| Senior FPGA Prototyping Engineer - Hardware | $196K - $368K |
| Senior ASIC Floorplan Design Engineer | $196,000 - $310,500 |
| Senior SRAM Engineer | $196,000 - $310,500 |
| Senior Manager, PR - AI Software | $196,000 - $310,500 |
Observed changes
- First observed on the employer's board
- Began meeting the published-salary criteria
- Observed since
- Employer-stated posting date
- 2026-10-30
Where this pay comes from
Location as the employer wrote it: US, CA, Santa Clara
base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary range for this position is 196,000 USD – 310,500 USD.
- Method
- Employer text, read with fixed rules and re-verified
- Checked
- Rule set
- us-base-v2
The pay passage appears in the employer's own job text. Fixed, deterministic rules located it, and the passage below was checked against the stored copy of the posting.
What we verified
- The pay figures come from the employer's own listing, quoted exactly above.
- The pay is an annual base salary in US dollars with a minimum of at least $100,000.
- The role was publicly listed on the employer's job board when last checked.
We do not verify what the employer will actually offer, whether the employer is still recruiting for the role, or anything beyond what the employer published. Full methodology.
